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https://github.com/bolucat/Archive.git
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Update On Mon Sep 30 20:38:22 CEST 2024
This commit is contained in:
github-action[bot]
-3447
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
-516
@@ -1,516 +0,0 @@
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||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include "rockchip-pinconf.dtsi"
|
||||
|
||||
/*
|
||||
* This file is auto generated by pin2dts tool, please keep these code
|
||||
* by adding changes at end of this file.
|
||||
*/
|
||||
&pinctrl {
|
||||
clk32k {
|
||||
/omit-if-no-ref/
|
||||
clk32k_out1: clk32k-out1 {
|
||||
rockchip,pins =
|
||||
/* clk32k_out1 */
|
||||
<2 RK_PC5 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
eth0 {
|
||||
/omit-if-no-ref/
|
||||
eth0_pins: eth0-pins {
|
||||
rockchip,pins =
|
||||
/* eth0_refclko_25m */
|
||||
<2 RK_PC3 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
fspi {
|
||||
/omit-if-no-ref/
|
||||
fspim1_pins: fspim1-pins {
|
||||
rockchip,pins =
|
||||
/* fspi_clk_m1 */
|
||||
<2 RK_PB3 3 &pcfg_pull_up_drv_level_2>,
|
||||
/* fspi_cs0n_m1 */
|
||||
<2 RK_PB4 3 &pcfg_pull_up_drv_level_2>,
|
||||
/* fspi_d0_m1 */
|
||||
<2 RK_PA6 3 &pcfg_pull_up_drv_level_2>,
|
||||
/* fspi_d1_m1 */
|
||||
<2 RK_PA7 3 &pcfg_pull_up_drv_level_2>,
|
||||
/* fspi_d2_m1 */
|
||||
<2 RK_PB0 3 &pcfg_pull_up_drv_level_2>,
|
||||
/* fspi_d3_m1 */
|
||||
<2 RK_PB1 3 &pcfg_pull_up_drv_level_2>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
fspim1_cs1: fspim1-cs1 {
|
||||
rockchip,pins =
|
||||
/* fspi_cs1n_m1 */
|
||||
<2 RK_PB5 3 &pcfg_pull_up_drv_level_2>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac0 {
|
||||
/omit-if-no-ref/
|
||||
gmac0_miim: gmac0-miim {
|
||||
rockchip,pins =
|
||||
/* gmac0_mdc */
|
||||
<4 RK_PC4 1 &pcfg_pull_none>,
|
||||
/* gmac0_mdio */
|
||||
<4 RK_PC5 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
gmac0_clkinout: gmac0-clkinout {
|
||||
rockchip,pins =
|
||||
/* gmac0_mclkinout */
|
||||
<4 RK_PC3 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
gmac0_rx_bus2: gmac0-rx-bus2 {
|
||||
rockchip,pins =
|
||||
/* gmac0_rxd0 */
|
||||
<2 RK_PC1 1 &pcfg_pull_none>,
|
||||
/* gmac0_rxd1 */
|
||||
<2 RK_PC2 1 &pcfg_pull_none>,
|
||||
/* gmac0_rxdv_crs */
|
||||
<4 RK_PC2 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
gmac0_tx_bus2: gmac0-tx-bus2 {
|
||||
rockchip,pins =
|
||||
/* gmac0_txd0 */
|
||||
<2 RK_PB6 1 &pcfg_pull_none>,
|
||||
/* gmac0_txd1 */
|
||||
<2 RK_PB7 1 &pcfg_pull_none>,
|
||||
/* gmac0_txen */
|
||||
<2 RK_PC0 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
gmac0_rgmii_clk: gmac0-rgmii-clk {
|
||||
rockchip,pins =
|
||||
/* gmac0_rxclk */
|
||||
<2 RK_PB0 1 &pcfg_pull_none>,
|
||||
/* gmac0_txclk */
|
||||
<2 RK_PB3 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
gmac0_rgmii_bus: gmac0-rgmii-bus {
|
||||
rockchip,pins =
|
||||
/* gmac0_rxd2 */
|
||||
<2 RK_PA6 1 &pcfg_pull_none>,
|
||||
/* gmac0_rxd3 */
|
||||
<2 RK_PA7 1 &pcfg_pull_none>,
|
||||
/* gmac0_txd2 */
|
||||
<2 RK_PB1 1 &pcfg_pull_none>,
|
||||
/* gmac0_txd3 */
|
||||
<2 RK_PB2 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
gmac0_ppsclk: gmac0-ppsclk {
|
||||
rockchip,pins =
|
||||
/* gmac0_ppsclk */
|
||||
<2 RK_PC4 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
gmac0_ppstring: gmac0-ppstring {
|
||||
rockchip,pins =
|
||||
/* gmac0_ppstring */
|
||||
<2 RK_PB5 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
gmac0_ptp_refclk: gmac0-ptp-refclk {
|
||||
rockchip,pins =
|
||||
/* gmac0_ptp_refclk */
|
||||
<2 RK_PB4 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
gmac0_txer: gmac0-txer {
|
||||
rockchip,pins =
|
||||
/* gmac0_txer */
|
||||
<4 RK_PC6 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
hdmi {
|
||||
/omit-if-no-ref/
|
||||
hdmim0_tx1_cec: hdmim0-tx1-cec {
|
||||
rockchip,pins =
|
||||
/* hdmim0_tx1_cec */
|
||||
<2 RK_PC4 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
hdmim0_tx1_scl: hdmim0-tx1-scl {
|
||||
rockchip,pins =
|
||||
/* hdmim0_tx1_scl */
|
||||
<2 RK_PB5 4 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
hdmim0_tx1_sda: hdmim0-tx1-sda {
|
||||
rockchip,pins =
|
||||
/* hdmim0_tx1_sda */
|
||||
<2 RK_PB4 4 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0 {
|
||||
/omit-if-no-ref/
|
||||
i2c0m1_xfer: i2c0m1-xfer {
|
||||
rockchip,pins =
|
||||
/* i2c0_scl_m1 */
|
||||
<4 RK_PC5 9 &pcfg_pull_none_smt>,
|
||||
/* i2c0_sda_m1 */
|
||||
<4 RK_PC6 9 &pcfg_pull_none_smt>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2 {
|
||||
/omit-if-no-ref/
|
||||
i2c2m1_xfer: i2c2m1-xfer {
|
||||
rockchip,pins =
|
||||
/* i2c2_scl_m1 */
|
||||
<2 RK_PC1 9 &pcfg_pull_none_smt>,
|
||||
/* i2c2_sda_m1 */
|
||||
<2 RK_PC0 9 &pcfg_pull_none_smt>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c3 {
|
||||
/omit-if-no-ref/
|
||||
i2c3m3_xfer: i2c3m3-xfer {
|
||||
rockchip,pins =
|
||||
/* i2c3_scl_m3 */
|
||||
<2 RK_PB2 9 &pcfg_pull_none_smt>,
|
||||
/* i2c3_sda_m3 */
|
||||
<2 RK_PB3 9 &pcfg_pull_none_smt>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c4 {
|
||||
/omit-if-no-ref/
|
||||
i2c4m1_xfer: i2c4m1-xfer {
|
||||
rockchip,pins =
|
||||
/* i2c4_scl_m1 */
|
||||
<2 RK_PB5 9 &pcfg_pull_none_smt>,
|
||||
/* i2c4_sda_m1 */
|
||||
<2 RK_PB4 9 &pcfg_pull_none_smt>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c5 {
|
||||
/omit-if-no-ref/
|
||||
i2c5m4_xfer: i2c5m4-xfer {
|
||||
rockchip,pins =
|
||||
/* i2c5_scl_m4 */
|
||||
<2 RK_PB6 9 &pcfg_pull_none_smt>,
|
||||
/* i2c5_sda_m4 */
|
||||
<2 RK_PB7 9 &pcfg_pull_none_smt>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c6 {
|
||||
/omit-if-no-ref/
|
||||
i2c6m2_xfer: i2c6m2-xfer {
|
||||
rockchip,pins =
|
||||
/* i2c6_scl_m2 */
|
||||
<2 RK_PC3 9 &pcfg_pull_none_smt>,
|
||||
/* i2c6_sda_m2 */
|
||||
<2 RK_PC2 9 &pcfg_pull_none_smt>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c7 {
|
||||
/omit-if-no-ref/
|
||||
i2c7m1_xfer: i2c7m1-xfer {
|
||||
rockchip,pins =
|
||||
/* i2c7_scl_m1 */
|
||||
<4 RK_PC3 9 &pcfg_pull_none_smt>,
|
||||
/* i2c7_sda_m1 */
|
||||
<4 RK_PC4 9 &pcfg_pull_none_smt>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c8 {
|
||||
/omit-if-no-ref/
|
||||
i2c8m1_xfer: i2c8m1-xfer {
|
||||
rockchip,pins =
|
||||
/* i2c8_scl_m1 */
|
||||
<2 RK_PB0 9 &pcfg_pull_none_smt>,
|
||||
/* i2c8_sda_m1 */
|
||||
<2 RK_PB1 9 &pcfg_pull_none_smt>;
|
||||
};
|
||||
};
|
||||
|
||||
i2s2 {
|
||||
/omit-if-no-ref/
|
||||
i2s2m0_lrck: i2s2m0-lrck {
|
||||
rockchip,pins =
|
||||
/* i2s2m0_lrck */
|
||||
<2 RK_PC0 2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s2m0_mclk: i2s2m0-mclk {
|
||||
rockchip,pins =
|
||||
/* i2s2m0_mclk */
|
||||
<2 RK_PB6 2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s2m0_sclk: i2s2m0-sclk {
|
||||
rockchip,pins =
|
||||
/* i2s2m0_sclk */
|
||||
<2 RK_PB7 2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s2m0_sdi: i2s2m0-sdi {
|
||||
rockchip,pins =
|
||||
/* i2s2m0_sdi */
|
||||
<2 RK_PC3 2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
i2s2m0_sdo: i2s2m0-sdo {
|
||||
rockchip,pins =
|
||||
/* i2s2m0_sdo */
|
||||
<4 RK_PC3 2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm2 {
|
||||
/omit-if-no-ref/
|
||||
pwm2m2_pins: pwm2m2-pins {
|
||||
rockchip,pins =
|
||||
/* pwm2_m2 */
|
||||
<4 RK_PC2 11 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm4 {
|
||||
/omit-if-no-ref/
|
||||
pwm4m1_pins: pwm4m1-pins {
|
||||
rockchip,pins =
|
||||
/* pwm4_m1 */
|
||||
<4 RK_PC3 11 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm5 {
|
||||
/omit-if-no-ref/
|
||||
pwm5m2_pins: pwm5m2-pins {
|
||||
rockchip,pins =
|
||||
/* pwm5_m2 */
|
||||
<4 RK_PC4 11 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm6 {
|
||||
/omit-if-no-ref/
|
||||
pwm6m2_pins: pwm6m2-pins {
|
||||
rockchip,pins =
|
||||
/* pwm6_m2 */
|
||||
<4 RK_PC5 11 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm7 {
|
||||
/omit-if-no-ref/
|
||||
pwm7m3_pins: pwm7m3-pins {
|
||||
rockchip,pins =
|
||||
/* pwm7_ir_m3 */
|
||||
<4 RK_PC6 11 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio {
|
||||
/omit-if-no-ref/
|
||||
sdiom0_pins: sdiom0-pins {
|
||||
rockchip,pins =
|
||||
/* sdio_clk_m0 */
|
||||
<2 RK_PB3 2 &pcfg_pull_none>,
|
||||
/* sdio_cmd_m0 */
|
||||
<2 RK_PB2 2 &pcfg_pull_none>,
|
||||
/* sdio_d0_m0 */
|
||||
<2 RK_PA6 2 &pcfg_pull_none>,
|
||||
/* sdio_d1_m0 */
|
||||
<2 RK_PA7 2 &pcfg_pull_none>,
|
||||
/* sdio_d2_m0 */
|
||||
<2 RK_PB0 2 &pcfg_pull_none>,
|
||||
/* sdio_d3_m0 */
|
||||
<2 RK_PB1 2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
spi1 {
|
||||
/omit-if-no-ref/
|
||||
spi1m0_pins: spi1m0-pins {
|
||||
rockchip,pins =
|
||||
/* spi1_clk_m0 */
|
||||
<2 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
|
||||
/* spi1_miso_m0 */
|
||||
<2 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
|
||||
/* spi1_mosi_m0 */
|
||||
<2 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
spi1m0_cs0: spi1m0-cs0 {
|
||||
rockchip,pins =
|
||||
/* spi1_cs0_m0 */
|
||||
<2 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
spi1m0_cs1: spi1m0-cs1 {
|
||||
rockchip,pins =
|
||||
/* spi1_cs1_m0 */
|
||||
<2 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
};
|
||||
|
||||
spi3 {
|
||||
/omit-if-no-ref/
|
||||
spi3m0_pins: spi3m0-pins {
|
||||
rockchip,pins =
|
||||
/* spi3_clk_m0 */
|
||||
<4 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
|
||||
/* spi3_miso_m0 */
|
||||
<4 RK_PC4 8 &pcfg_pull_up_drv_level_1>,
|
||||
/* spi3_mosi_m0 */
|
||||
<4 RK_PC5 8 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
spi3m0_cs0: spi3m0-cs0 {
|
||||
rockchip,pins =
|
||||
/* spi3_cs0_m0 */
|
||||
<4 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
spi3m0_cs1: spi3m0-cs1 {
|
||||
rockchip,pins =
|
||||
/* spi3_cs1_m0 */
|
||||
<4 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
/omit-if-no-ref/
|
||||
uart1m0_xfer: uart1m0-xfer {
|
||||
rockchip,pins =
|
||||
/* uart1_rx_m0 */
|
||||
<2 RK_PB6 10 &pcfg_pull_up>,
|
||||
/* uart1_tx_m0 */
|
||||
<2 RK_PB7 10 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
uart1m0_ctsn: uart1m0-ctsn {
|
||||
rockchip,pins =
|
||||
/* uart1m0_ctsn */
|
||||
<2 RK_PC1 10 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
uart1m0_rtsn: uart1m0-rtsn {
|
||||
rockchip,pins =
|
||||
/* uart1m0_rtsn */
|
||||
<2 RK_PC0 10 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart6 {
|
||||
/omit-if-no-ref/
|
||||
uart6m0_xfer: uart6m0-xfer {
|
||||
rockchip,pins =
|
||||
/* uart6_rx_m0 */
|
||||
<2 RK_PA6 10 &pcfg_pull_up>,
|
||||
/* uart6_tx_m0 */
|
||||
<2 RK_PA7 10 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
uart6m0_ctsn: uart6m0-ctsn {
|
||||
rockchip,pins =
|
||||
/* uart6m0_ctsn */
|
||||
<2 RK_PB1 10 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
uart6m0_rtsn: uart6m0-rtsn {
|
||||
rockchip,pins =
|
||||
/* uart6m0_rtsn */
|
||||
<2 RK_PB0 10 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart7 {
|
||||
/omit-if-no-ref/
|
||||
uart7m0_xfer: uart7m0-xfer {
|
||||
rockchip,pins =
|
||||
/* uart7_rx_m0 */
|
||||
<2 RK_PB4 10 &pcfg_pull_up>,
|
||||
/* uart7_tx_m0 */
|
||||
<2 RK_PB5 10 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
uart7m0_ctsn: uart7m0-ctsn {
|
||||
rockchip,pins =
|
||||
/* uart7m0_ctsn */
|
||||
<4 RK_PC6 10 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
uart7m0_rtsn: uart7m0-rtsn {
|
||||
rockchip,pins =
|
||||
/* uart7m0_rtsn */
|
||||
<4 RK_PC2 10 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart9 {
|
||||
/omit-if-no-ref/
|
||||
uart9m0_xfer: uart9m0-xfer {
|
||||
rockchip,pins =
|
||||
/* uart9_rx_m0 */
|
||||
<2 RK_PC4 10 &pcfg_pull_up>,
|
||||
/* uart9_tx_m0 */
|
||||
<2 RK_PC2 10 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
uart9m0_ctsn: uart9m0-ctsn {
|
||||
rockchip,pins =
|
||||
/* uart9m0_ctsn */
|
||||
<4 RK_PC5 10 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
uart9m0_rtsn: uart9m0-rtsn {
|
||||
rockchip,pins =
|
||||
/* uart9m0_rtsn */
|
||||
<4 RK_PC4 10 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,448 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#include "rk3588-base.dtsi"
|
||||
#include "rk3588-extra-pinctrl.dtsi"
|
||||
|
||||
/ {
|
||||
usb_host1_xhci: usb@fc400000 {
|
||||
compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
|
||||
reg = <0x0 0xfc400000 0x0 0x400000>;
|
||||
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
|
||||
<&cru ACLK_USB3OTG1>;
|
||||
clock-names = "ref_clk", "suspend_clk", "bus_clk";
|
||||
dr_mode = "otg";
|
||||
phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
phy_type = "utmi_wide";
|
||||
power-domains = <&power RK3588_PD_USB>;
|
||||
resets = <&cru SRST_A_USB3OTG1>;
|
||||
snps,dis_enblslpm_quirk;
|
||||
snps,dis-u2-freeclk-exists-quirk;
|
||||
snps,dis-del-phy-power-chg-quirk;
|
||||
snps,dis-tx-ipgap-linecheck-quirk;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie30_phy_grf: syscon@fd5b8000 {
|
||||
compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
|
||||
reg = <0x0 0xfd5b8000 0x0 0x10000>;
|
||||
};
|
||||
|
||||
pipe_phy1_grf: syscon@fd5c0000 {
|
||||
compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
|
||||
reg = <0x0 0xfd5c0000 0x0 0x100>;
|
||||
};
|
||||
|
||||
usbdpphy1_grf: syscon@fd5cc000 {
|
||||
compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
|
||||
reg = <0x0 0xfd5cc000 0x0 0x4000>;
|
||||
};
|
||||
|
||||
usb2phy1_grf: syscon@fd5d4000 {
|
||||
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xfd5d4000 0x0 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
u2phy1: usb2phy@4000 {
|
||||
compatible = "rockchip,rk3588-usb2phy";
|
||||
reg = <0x4000 0x10>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
||||
clock-names = "phyclk";
|
||||
clock-output-names = "usb480m_phy1";
|
||||
interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
|
||||
reset-names = "phy", "apb";
|
||||
status = "disabled";
|
||||
|
||||
u2phy1_otg: otg-port {
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2s8_8ch: i2s@fddc8000 {
|
||||
compatible = "rockchip,rk3588-i2s-tdm";
|
||||
reg = <0x0 0xfddc8000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
|
||||
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
||||
assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
|
||||
assigned-clock-parents = <&cru PLL_AUPLL>;
|
||||
dmas = <&dmac2 22>;
|
||||
dma-names = "tx";
|
||||
power-domains = <&power RK3588_PD_VO0>;
|
||||
resets = <&cru SRST_M_I2S8_8CH_TX>;
|
||||
reset-names = "tx-m";
|
||||
#sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2s6_8ch: i2s@fddf4000 {
|
||||
compatible = "rockchip,rk3588-i2s-tdm";
|
||||
reg = <0x0 0xfddf4000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
|
||||
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
||||
assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
|
||||
assigned-clock-parents = <&cru PLL_AUPLL>;
|
||||
dmas = <&dmac2 4>;
|
||||
dma-names = "tx";
|
||||
power-domains = <&power RK3588_PD_VO1>;
|
||||
resets = <&cru SRST_M_I2S6_8CH_TX>;
|
||||
reset-names = "tx-m";
|
||||
#sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2s7_8ch: i2s@fddf8000 {
|
||||
compatible = "rockchip,rk3588-i2s-tdm";
|
||||
reg = <0x0 0xfddf8000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
|
||||
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
||||
assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
|
||||
assigned-clock-parents = <&cru PLL_AUPLL>;
|
||||
dmas = <&dmac2 21>;
|
||||
dma-names = "rx";
|
||||
power-domains = <&power RK3588_PD_VO1>;
|
||||
resets = <&cru SRST_M_I2S7_8CH_RX>;
|
||||
reset-names = "rx-m";
|
||||
#sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2s10_8ch: i2s@fde00000 {
|
||||
compatible = "rockchip,rk3588-i2s-tdm";
|
||||
reg = <0x0 0xfde00000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
|
||||
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
||||
assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
|
||||
assigned-clock-parents = <&cru PLL_AUPLL>;
|
||||
dmas = <&dmac2 24>;
|
||||
dma-names = "rx";
|
||||
power-domains = <&power RK3588_PD_VO1>;
|
||||
resets = <&cru SRST_M_I2S10_8CH_RX>;
|
||||
reset-names = "rx-m";
|
||||
#sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie3x4: pcie@fe150000 {
|
||||
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x00 0x0f>;
|
||||
clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
|
||||
<&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
|
||||
<&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk",
|
||||
"aux", "pipe";
|
||||
device_type = "pci";
|
||||
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
|
||||
<0 0 0 2 &pcie3x4_intc 1>,
|
||||
<0 0 0 3 &pcie3x4_intc 2>,
|
||||
<0 0 0 4 &pcie3x4_intc 3>;
|
||||
linux,pci-domain = <0>;
|
||||
max-link-speed = <3>;
|
||||
msi-map = <0x0000 &its1 0x0000 0x1000>;
|
||||
num-lanes = <4>;
|
||||
phys = <&pcie30phy>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3588_PD_PCIE>;
|
||||
ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
|
||||
<0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
|
||||
<0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
|
||||
reg = <0xa 0x40000000 0x0 0x00400000>,
|
||||
<0x0 0xfe150000 0x0 0x00010000>,
|
||||
<0x0 0xf0000000 0x0 0x00100000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
|
||||
reset-names = "pwr", "pipe";
|
||||
status = "disabled";
|
||||
|
||||
pcie3x4_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie3x4_ep: pcie-ep@fe150000 {
|
||||
compatible = "rockchip,rk3588-pcie-ep";
|
||||
reg = <0xa 0x40000000 0x0 0x00100000>,
|
||||
<0xa 0x40100000 0x0 0x00100000>,
|
||||
<0x0 0xfe150000 0x0 0x00010000>,
|
||||
<0x9 0x00000000 0x0 0x40000000>,
|
||||
<0xa 0x40300000 0x0 0x00100000>;
|
||||
reg-names = "dbi", "dbi2", "apb", "addr_space", "atu";
|
||||
clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
|
||||
<&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
|
||||
<&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk",
|
||||
"aux", "pipe";
|
||||
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "sys", "pmc", "msg", "legacy", "err",
|
||||
"dma0", "dma1", "dma2", "dma3";
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <4>;
|
||||
phys = <&pcie30phy>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3588_PD_PCIE>;
|
||||
resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
|
||||
reset-names = "pwr", "pipe";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie3x2: pcie@fe160000 {
|
||||
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x10 0x1f>;
|
||||
clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
|
||||
<&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
|
||||
<&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk",
|
||||
"aux", "pipe";
|
||||
device_type = "pci";
|
||||
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
|
||||
<0 0 0 2 &pcie3x2_intc 1>,
|
||||
<0 0 0 3 &pcie3x2_intc 2>,
|
||||
<0 0 0 4 &pcie3x2_intc 3>;
|
||||
linux,pci-domain = <1>;
|
||||
max-link-speed = <3>;
|
||||
msi-map = <0x1000 &its1 0x1000 0x1000>;
|
||||
num-lanes = <2>;
|
||||
phys = <&pcie30phy>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3588_PD_PCIE>;
|
||||
ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
|
||||
<0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
|
||||
<0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
|
||||
reg = <0xa 0x40400000 0x0 0x00400000>,
|
||||
<0x0 0xfe160000 0x0 0x00010000>,
|
||||
<0x0 0xf1000000 0x0 0x00100000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
|
||||
reset-names = "pwr", "pipe";
|
||||
status = "disabled";
|
||||
|
||||
pcie3x2_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2x1l0: pcie@fe170000 {
|
||||
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
||||
bus-range = <0x20 0x2f>;
|
||||
clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
|
||||
<&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
|
||||
<&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk",
|
||||
"aux", "pipe";
|
||||
device_type = "pci";
|
||||
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
|
||||
<0 0 0 2 &pcie2x1l0_intc 1>,
|
||||
<0 0 0 3 &pcie2x1l0_intc 2>,
|
||||
<0 0 0 4 &pcie2x1l0_intc 3>;
|
||||
linux,pci-domain = <2>;
|
||||
max-link-speed = <2>;
|
||||
msi-map = <0x2000 &its0 0x2000 0x1000>;
|
||||
num-lanes = <1>;
|
||||
phys = <&combphy1_ps PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3588_PD_PCIE>;
|
||||
ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
|
||||
<0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
|
||||
<0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
|
||||
reg = <0xa 0x40800000 0x0 0x00400000>,
|
||||
<0x0 0xfe170000 0x0 0x00010000>,
|
||||
<0x0 0xf2000000 0x0 0x00100000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
|
||||
reset-names = "pwr", "pipe";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
status = "disabled";
|
||||
|
||||
pcie2x1l0_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac0: ethernet@fe1b0000 {
|
||||
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
|
||||
reg = <0x0 0xfe1b0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "macirq", "eth_wake_irq";
|
||||
clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
|
||||
<&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
|
||||
<&cru CLK_GMAC0_PTP_REF>;
|
||||
clock-names = "stmmaceth", "clk_mac_ref",
|
||||
"pclk_mac", "aclk_mac",
|
||||
"ptp_ref";
|
||||
power-domains = <&power RK3588_PD_GMAC>;
|
||||
resets = <&cru SRST_A_GMAC0>;
|
||||
reset-names = "stmmaceth";
|
||||
rockchip,grf = <&sys_grf>;
|
||||
rockchip,php-grf = <&php_grf>;
|
||||
snps,axi-config = <&gmac0_stmmac_axi_setup>;
|
||||
snps,mixed-burst;
|
||||
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
|
||||
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
|
||||
snps,tso;
|
||||
status = "disabled";
|
||||
|
||||
mdio0: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
};
|
||||
|
||||
gmac0_stmmac_axi_setup: stmmac-axi-config {
|
||||
snps,blen = <0 0 0 0 16 8 4>;
|
||||
snps,wr_osr_lmt = <4>;
|
||||
snps,rd_osr_lmt = <8>;
|
||||
};
|
||||
|
||||
gmac0_mtl_rx_setup: rx-queues-config {
|
||||
snps,rx-queues-to-use = <2>;
|
||||
queue0 {};
|
||||
queue1 {};
|
||||
};
|
||||
|
||||
gmac0_mtl_tx_setup: tx-queues-config {
|
||||
snps,tx-queues-to-use = <2>;
|
||||
queue0 {};
|
||||
queue1 {};
|
||||
};
|
||||
};
|
||||
|
||||
sata1: sata@fe220000 {
|
||||
compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
|
||||
reg = <0 0xfe220000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
|
||||
<&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
|
||||
<&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
|
||||
clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
|
||||
ports-implemented = <0x1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
sata-port@0 {
|
||||
reg = <0>;
|
||||
hba-port-cap = <HBA_PORT_FBSCP>;
|
||||
phys = <&combphy1_ps PHY_TYPE_SATA>;
|
||||
phy-names = "sata-phy";
|
||||
snps,rx-ts-max = <32>;
|
||||
snps,tx-ts-max = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
usbdp_phy1: phy@fed90000 {
|
||||
compatible = "rockchip,rk3588-usbdp-phy";
|
||||
reg = <0x0 0xfed90000 0x0 0x10000>;
|
||||
#phy-cells = <1>;
|
||||
clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
|
||||
<&cru CLK_USBDP_PHY1_IMMORTAL>,
|
||||
<&cru PCLK_USBDPPHY1>,
|
||||
<&u2phy1>;
|
||||
clock-names = "refclk", "immortal", "pclk", "utmi";
|
||||
resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
|
||||
<&cru SRST_USBDP_COMBO_PHY1_CMN>,
|
||||
<&cru SRST_USBDP_COMBO_PHY1_LANE>,
|
||||
<&cru SRST_USBDP_COMBO_PHY1_PCS>,
|
||||
<&cru SRST_P_USBDPPHY1>;
|
||||
reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
|
||||
rockchip,u2phy-grf = <&usb2phy1_grf>;
|
||||
rockchip,usb-grf = <&usb_grf>;
|
||||
rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
|
||||
rockchip,vo-grf = <&vo0_grf>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
combphy1_ps: phy@fee10000 {
|
||||
compatible = "rockchip,rk3588-naneng-combphy";
|
||||
reg = <0x0 0xfee10000 0x0 0x100>;
|
||||
clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
|
||||
<&cru PCLK_PHP_ROOT>;
|
||||
clock-names = "ref", "apb", "pipe";
|
||||
assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
#phy-cells = <1>;
|
||||
resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;
|
||||
reset-names = "phy", "apb";
|
||||
rockchip,pipe-grf = <&php_grf>;
|
||||
rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie30phy: phy@fee80000 {
|
||||
compatible = "rockchip,rk3588-pcie3-phy";
|
||||
reg = <0x0 0xfee80000 0x0 0x20000>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
|
||||
clock-names = "pclk";
|
||||
resets = <&cru SRST_PCIE30_PHY>;
|
||||
reset-names = "phy";
|
||||
rockchip,pipe-grf = <&php_grf>;
|
||||
rockchip,phy-grf = <&pcie30_phy_grf>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
@@ -1,190 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/ {
|
||||
cluster0_opp_table: opp-table-cluster0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-1008000000 {
|
||||
opp-hz = /bits/ 64 <1008000000>;
|
||||
opp-microvolt = <675000 675000 950000>;
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
opp-1200000000 {
|
||||
opp-hz = /bits/ 64 <1200000000>;
|
||||
opp-microvolt = <712500 712500 950000>;
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
opp-1416000000 {
|
||||
opp-hz = /bits/ 64 <1416000000>;
|
||||
opp-microvolt = <762500 762500 950000>;
|
||||
clock-latency-ns = <40000>;
|
||||
opp-suspend;
|
||||
};
|
||||
opp-1608000000 {
|
||||
opp-hz = /bits/ 64 <1608000000>;
|
||||
opp-microvolt = <850000 850000 950000>;
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
opp-1800000000 {
|
||||
opp-hz = /bits/ 64 <1800000000>;
|
||||
opp-microvolt = <950000 950000 950000>;
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1_opp_table: opp-table-cluster1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-1200000000 {
|
||||
opp-hz = /bits/ 64 <1200000000>;
|
||||
opp-microvolt = <675000 675000 1000000>;
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
opp-1416000000 {
|
||||
opp-hz = /bits/ 64 <1416000000>;
|
||||
opp-microvolt = <725000 725000 1000000>;
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
opp-1608000000 {
|
||||
opp-hz = /bits/ 64 <1608000000>;
|
||||
opp-microvolt = <762500 762500 1000000>;
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
opp-1800000000 {
|
||||
opp-hz = /bits/ 64 <1800000000>;
|
||||
opp-microvolt = <850000 850000 1000000>;
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
opp-2016000000 {
|
||||
opp-hz = /bits/ 64 <2016000000>;
|
||||
opp-microvolt = <925000 925000 1000000>;
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
opp-2208000000 {
|
||||
opp-hz = /bits/ 64 <2208000000>;
|
||||
opp-microvolt = <987500 987500 1000000>;
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
opp-2400000000 {
|
||||
opp-hz = /bits/ 64 <2400000000>;
|
||||
opp-microvolt = <1000000 1000000 1000000>;
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster2_opp_table: opp-table-cluster2 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-1200000000 {
|
||||
opp-hz = /bits/ 64 <1200000000>;
|
||||
opp-microvolt = <675000 675000 1000000>;
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
opp-1416000000 {
|
||||
opp-hz = /bits/ 64 <1416000000>;
|
||||
opp-microvolt = <725000 725000 1000000>;
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
opp-1608000000 {
|
||||
opp-hz = /bits/ 64 <1608000000>;
|
||||
opp-microvolt = <762500 762500 1000000>;
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
opp-1800000000 {
|
||||
opp-hz = /bits/ 64 <1800000000>;
|
||||
opp-microvolt = <850000 850000 1000000>;
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
opp-2016000000 {
|
||||
opp-hz = /bits/ 64 <2016000000>;
|
||||
opp-microvolt = <925000 925000 1000000>;
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
opp-2208000000 {
|
||||
opp-hz = /bits/ 64 <2208000000>;
|
||||
opp-microvolt = <987500 987500 1000000>;
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
opp-2400000000 {
|
||||
opp-hz = /bits/ 64 <2400000000>;
|
||||
opp-microvolt = <1000000 1000000 1000000>;
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
};
|
||||
|
||||
gpu_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
opp-microvolt = <675000 675000 850000>;
|
||||
};
|
||||
opp-400000000 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
opp-microvolt = <675000 675000 850000>;
|
||||
};
|
||||
opp-500000000 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
opp-microvolt = <675000 675000 850000>;
|
||||
};
|
||||
opp-600000000 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-microvolt = <675000 675000 850000>;
|
||||
};
|
||||
opp-700000000 {
|
||||
opp-hz = /bits/ 64 <700000000>;
|
||||
opp-microvolt = <700000 700000 850000>;
|
||||
};
|
||||
opp-800000000 {
|
||||
opp-hz = /bits/ 64 <800000000>;
|
||||
opp-microvolt = <750000 750000 850000>;
|
||||
};
|
||||
opp-900000000 {
|
||||
opp-hz = /bits/ 64 <900000000>;
|
||||
opp-microvolt = <800000 800000 850000>;
|
||||
};
|
||||
opp-1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-microvolt = <850000 850000 850000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_b0 {
|
||||
operating-points-v2 = <&cluster1_opp_table>;
|
||||
};
|
||||
|
||||
&cpu_b1 {
|
||||
operating-points-v2 = <&cluster1_opp_table>;
|
||||
};
|
||||
|
||||
&cpu_b2 {
|
||||
operating-points-v2 = <&cluster2_opp_table>;
|
||||
};
|
||||
|
||||
&cpu_b3 {
|
||||
operating-points-v2 = <&cluster2_opp_table>;
|
||||
};
|
||||
|
||||
&cpu_l0 {
|
||||
operating-points-v2 = <&cluster0_opp_table>;
|
||||
};
|
||||
|
||||
&cpu_l1 {
|
||||
operating-points-v2 = <&cluster0_opp_table>;
|
||||
};
|
||||
|
||||
&cpu_l2 {
|
||||
operating-points-v2 = <&cluster0_opp_table>;
|
||||
};
|
||||
|
||||
&cpu_l3 {
|
||||
operating-points-v2 = <&cluster0_opp_table>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
operating-points-v2 = <&gpu_opp_table>;
|
||||
};
|
||||
@@ -1,8 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "rk3588-extra.dtsi"
|
||||
#include "rk3588-opp.dtsi"
|
||||
@@ -1,20 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
|
||||
/*
|
||||
* This header provides constants for most AHCI bindings.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_ATA_AHCI_H
|
||||
#define _DT_BINDINGS_ATA_AHCI_H
|
||||
|
||||
/* Host Bus Adapter generic platform capabilities */
|
||||
#define HBA_SSS (1 << 27)
|
||||
#define HBA_SMPS (1 << 28)
|
||||
|
||||
/* Host Bus Adapter port-specific platform capabilities */
|
||||
#define HBA_PORT_HPCP (1 << 18)
|
||||
#define HBA_PORT_MPSP (1 << 19)
|
||||
#define HBA_PORT_CPD (1 << 20)
|
||||
#define HBA_PORT_ESP (1 << 21)
|
||||
#define HBA_PORT_FBSCP (1 << 22)
|
||||
|
||||
#endif
|
||||
-765
@@ -1,765 +0,0 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
|
||||
* Copyright (c) 2022 Collabora Ltd.
|
||||
*
|
||||
* Author: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
* Author: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H
|
||||
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H
|
||||
|
||||
/* cru-clocks indices */
|
||||
|
||||
#define PLL_B0PLL 0
|
||||
#define PLL_B1PLL 1
|
||||
#define PLL_LPLL 2
|
||||
#define PLL_V0PLL 3
|
||||
#define PLL_AUPLL 4
|
||||
#define PLL_CPLL 5
|
||||
#define PLL_GPLL 6
|
||||
#define PLL_NPLL 7
|
||||
#define PLL_PPLL 8
|
||||
#define ARMCLK_L 9
|
||||
#define ARMCLK_B01 10
|
||||
#define ARMCLK_B23 11
|
||||
#define PCLK_BIGCORE0_ROOT 12
|
||||
#define PCLK_BIGCORE0_PVTM 13
|
||||
#define PCLK_BIGCORE1_ROOT 14
|
||||
#define PCLK_BIGCORE1_PVTM 15
|
||||
#define PCLK_DSU_S_ROOT 16
|
||||
#define PCLK_DSU_ROOT 17
|
||||
#define PCLK_DSU_NS_ROOT 18
|
||||
#define PCLK_LITCORE_PVTM 19
|
||||
#define PCLK_DBG 20
|
||||
#define PCLK_DSU 21
|
||||
#define PCLK_S_DAPLITE 22
|
||||
#define PCLK_M_DAPLITE 23
|
||||
#define MBIST_MCLK_PDM1 24
|
||||
#define MBIST_CLK_ACDCDIG 25
|
||||
#define HCLK_I2S2_2CH 26
|
||||
#define HCLK_I2S3_2CH 27
|
||||
#define CLK_I2S2_2CH_SRC 28
|
||||
#define CLK_I2S2_2CH_FRAC 29
|
||||
#define CLK_I2S2_2CH 30
|
||||
#define MCLK_I2S2_2CH 31
|
||||
#define I2S2_2CH_MCLKOUT 32
|
||||
#define CLK_DAC_ACDCDIG 33
|
||||
#define CLK_I2S3_2CH_SRC 34
|
||||
#define CLK_I2S3_2CH_FRAC 35
|
||||
#define CLK_I2S3_2CH 36
|
||||
#define MCLK_I2S3_2CH 37
|
||||
#define I2S3_2CH_MCLKOUT 38
|
||||
#define PCLK_ACDCDIG 39
|
||||
#define HCLK_I2S0_8CH 40
|
||||
#define CLK_I2S0_8CH_TX_SRC 41
|
||||
#define CLK_I2S0_8CH_TX_FRAC 42
|
||||
#define MCLK_I2S0_8CH_TX 43
|
||||
#define CLK_I2S0_8CH_TX 44
|
||||
#define CLK_I2S0_8CH_RX_SRC 45
|
||||
#define CLK_I2S0_8CH_RX_FRAC 46
|
||||
#define MCLK_I2S0_8CH_RX 47
|
||||
#define CLK_I2S0_8CH_RX 48
|
||||
#define I2S0_8CH_MCLKOUT 49
|
||||
#define HCLK_PDM1 50
|
||||
#define MCLK_PDM1 51
|
||||
#define HCLK_AUDIO_ROOT 52
|
||||
#define PCLK_AUDIO_ROOT 53
|
||||
#define HCLK_SPDIF0 54
|
||||
#define CLK_SPDIF0_SRC 55
|
||||
#define CLK_SPDIF0_FRAC 56
|
||||
#define MCLK_SPDIF0 57
|
||||
#define CLK_SPDIF0 58
|
||||
#define CLK_SPDIF1 59
|
||||
#define HCLK_SPDIF1 60
|
||||
#define CLK_SPDIF1_SRC 61
|
||||
#define CLK_SPDIF1_FRAC 62
|
||||
#define MCLK_SPDIF1 63
|
||||
#define ACLK_AV1_ROOT 64
|
||||
#define ACLK_AV1 65
|
||||
#define PCLK_AV1_ROOT 66
|
||||
#define PCLK_AV1 67
|
||||
#define PCLK_MAILBOX0 68
|
||||
#define PCLK_MAILBOX1 69
|
||||
#define PCLK_MAILBOX2 70
|
||||
#define PCLK_PMU2 71
|
||||
#define PCLK_PMUCM0_INTMUX 72
|
||||
#define PCLK_DDRCM0_INTMUX 73
|
||||
#define PCLK_TOP 74
|
||||
#define PCLK_PWM1 75
|
||||
#define CLK_PWM1 76
|
||||
#define CLK_PWM1_CAPTURE 77
|
||||
#define PCLK_PWM2 78
|
||||
#define CLK_PWM2 79
|
||||
#define CLK_PWM2_CAPTURE 80
|
||||
#define PCLK_PWM3 81
|
||||
#define CLK_PWM3 82
|
||||
#define CLK_PWM3_CAPTURE 83
|
||||
#define PCLK_BUSTIMER0 84
|
||||
#define PCLK_BUSTIMER1 85
|
||||
#define CLK_BUS_TIMER_ROOT 86
|
||||
#define CLK_BUSTIMER0 87
|
||||
#define CLK_BUSTIMER1 88
|
||||
#define CLK_BUSTIMER2 89
|
||||
#define CLK_BUSTIMER3 90
|
||||
#define CLK_BUSTIMER4 91
|
||||
#define CLK_BUSTIMER5 92
|
||||
#define CLK_BUSTIMER6 93
|
||||
#define CLK_BUSTIMER7 94
|
||||
#define CLK_BUSTIMER8 95
|
||||
#define CLK_BUSTIMER9 96
|
||||
#define CLK_BUSTIMER10 97
|
||||
#define CLK_BUSTIMER11 98
|
||||
#define PCLK_WDT0 99
|
||||
#define TCLK_WDT0 100
|
||||
#define PCLK_CAN0 101
|
||||
#define CLK_CAN0 102
|
||||
#define PCLK_CAN1 103
|
||||
#define CLK_CAN1 104
|
||||
#define PCLK_CAN2 105
|
||||
#define CLK_CAN2 106
|
||||
#define ACLK_DECOM 107
|
||||
#define PCLK_DECOM 108
|
||||
#define DCLK_DECOM 109
|
||||
#define ACLK_DMAC0 110
|
||||
#define ACLK_DMAC1 111
|
||||
#define ACLK_DMAC2 112
|
||||
#define ACLK_BUS_ROOT 113
|
||||
#define ACLK_GIC 114
|
||||
#define PCLK_GPIO1 115
|
||||
#define DBCLK_GPIO1 116
|
||||
#define PCLK_GPIO2 117
|
||||
#define DBCLK_GPIO2 118
|
||||
#define PCLK_GPIO3 119
|
||||
#define DBCLK_GPIO3 120
|
||||
#define PCLK_GPIO4 121
|
||||
#define DBCLK_GPIO4 122
|
||||
#define PCLK_I2C1 123
|
||||
#define PCLK_I2C2 124
|
||||
#define PCLK_I2C3 125
|
||||
#define PCLK_I2C4 126
|
||||
#define PCLK_I2C5 127
|
||||
#define PCLK_I2C6 128
|
||||
#define PCLK_I2C7 129
|
||||
#define PCLK_I2C8 130
|
||||
#define CLK_I2C1 131
|
||||
#define CLK_I2C2 132
|
||||
#define CLK_I2C3 133
|
||||
#define CLK_I2C4 134
|
||||
#define CLK_I2C5 135
|
||||
#define CLK_I2C6 136
|
||||
#define CLK_I2C7 137
|
||||
#define CLK_I2C8 138
|
||||
#define PCLK_OTPC_NS 139
|
||||
#define CLK_OTPC_NS 140
|
||||
#define CLK_OTPC_ARB 141
|
||||
#define CLK_OTPC_AUTO_RD_G 142
|
||||
#define CLK_OTP_PHY_G 143
|
||||
#define PCLK_SARADC 144
|
||||
#define CLK_SARADC 145
|
||||
#define PCLK_SPI0 146
|
||||
#define PCLK_SPI1 147
|
||||
#define PCLK_SPI2 148
|
||||
#define PCLK_SPI3 149
|
||||
#define PCLK_SPI4 150
|
||||
#define CLK_SPI0 151
|
||||
#define CLK_SPI1 152
|
||||
#define CLK_SPI2 153
|
||||
#define CLK_SPI3 154
|
||||
#define CLK_SPI4 155
|
||||
#define ACLK_SPINLOCK 156
|
||||
#define PCLK_TSADC 157
|
||||
#define CLK_TSADC 158
|
||||
#define PCLK_UART1 159
|
||||
#define PCLK_UART2 160
|
||||
#define PCLK_UART3 161
|
||||
#define PCLK_UART4 162
|
||||
#define PCLK_UART5 163
|
||||
#define PCLK_UART6 164
|
||||
#define PCLK_UART7 165
|
||||
#define PCLK_UART8 166
|
||||
#define PCLK_UART9 167
|
||||
#define CLK_UART1_SRC 168
|
||||
#define CLK_UART1_FRAC 169
|
||||
#define CLK_UART1 170
|
||||
#define SCLK_UART1 171
|
||||
#define CLK_UART2_SRC 172
|
||||
#define CLK_UART2_FRAC 173
|
||||
#define CLK_UART2 174
|
||||
#define SCLK_UART2 175
|
||||
#define CLK_UART3_SRC 176
|
||||
#define CLK_UART3_FRAC 177
|
||||
#define CLK_UART3 178
|
||||
#define SCLK_UART3 179
|
||||
#define CLK_UART4_SRC 180
|
||||
#define CLK_UART4_FRAC 181
|
||||
#define CLK_UART4 182
|
||||
#define SCLK_UART4 183
|
||||
#define CLK_UART5_SRC 184
|
||||
#define CLK_UART5_FRAC 185
|
||||
#define CLK_UART5 186
|
||||
#define SCLK_UART5 187
|
||||
#define CLK_UART6_SRC 188
|
||||
#define CLK_UART6_FRAC 189
|
||||
#define CLK_UART6 190
|
||||
#define SCLK_UART6 191
|
||||
#define CLK_UART7_SRC 192
|
||||
#define CLK_UART7_FRAC 193
|
||||
#define CLK_UART7 194
|
||||
#define SCLK_UART7 195
|
||||
#define CLK_UART8_SRC 196
|
||||
#define CLK_UART8_FRAC 197
|
||||
#define CLK_UART8 198
|
||||
#define SCLK_UART8 199
|
||||
#define CLK_UART9_SRC 200
|
||||
#define CLK_UART9_FRAC 201
|
||||
#define CLK_UART9 202
|
||||
#define SCLK_UART9 203
|
||||
#define ACLK_CENTER_ROOT 204
|
||||
#define ACLK_CENTER_LOW_ROOT 205
|
||||
#define HCLK_CENTER_ROOT 206
|
||||
#define PCLK_CENTER_ROOT 207
|
||||
#define ACLK_DMA2DDR 208
|
||||
#define ACLK_DDR_SHAREMEM 209
|
||||
#define ACLK_CENTER_S200_ROOT 210
|
||||
#define ACLK_CENTER_S400_ROOT 211
|
||||
#define FCLK_DDR_CM0_CORE 212
|
||||
#define CLK_DDR_TIMER_ROOT 213
|
||||
#define CLK_DDR_TIMER0 214
|
||||
#define CLK_DDR_TIMER1 215
|
||||
#define TCLK_WDT_DDR 216
|
||||
#define CLK_DDR_CM0_RTC 217
|
||||
#define PCLK_WDT 218
|
||||
#define PCLK_TIMER 219
|
||||
#define PCLK_DMA2DDR 220
|
||||
#define PCLK_SHAREMEM 221
|
||||
#define CLK_50M_SRC 222
|
||||
#define CLK_100M_SRC 223
|
||||
#define CLK_150M_SRC 224
|
||||
#define CLK_200M_SRC 225
|
||||
#define CLK_250M_SRC 226
|
||||
#define CLK_300M_SRC 227
|
||||
#define CLK_350M_SRC 228
|
||||
#define CLK_400M_SRC 229
|
||||
#define CLK_450M_SRC 230
|
||||
#define CLK_500M_SRC 231
|
||||
#define CLK_600M_SRC 232
|
||||
#define CLK_650M_SRC 233
|
||||
#define CLK_700M_SRC 234
|
||||
#define CLK_800M_SRC 235
|
||||
#define CLK_1000M_SRC 236
|
||||
#define CLK_1200M_SRC 237
|
||||
#define ACLK_TOP_M300_ROOT 238
|
||||
#define ACLK_TOP_M500_ROOT 239
|
||||
#define ACLK_TOP_M400_ROOT 240
|
||||
#define ACLK_TOP_S200_ROOT 241
|
||||
#define ACLK_TOP_S400_ROOT 242
|
||||
#define CLK_MIPI_CAMARAOUT_M0 243
|
||||
#define CLK_MIPI_CAMARAOUT_M1 244
|
||||
#define CLK_MIPI_CAMARAOUT_M2 245
|
||||
#define CLK_MIPI_CAMARAOUT_M3 246
|
||||
#define CLK_MIPI_CAMARAOUT_M4 247
|
||||
#define MCLK_GMAC0_OUT 248
|
||||
#define REFCLKO25M_ETH0_OUT 249
|
||||
#define REFCLKO25M_ETH1_OUT 250
|
||||
#define CLK_CIFOUT_OUT 251
|
||||
#define PCLK_MIPI_DCPHY0 252
|
||||
#define PCLK_MIPI_DCPHY1 253
|
||||
#define PCLK_CSIPHY0 254
|
||||
#define PCLK_CSIPHY1 255
|
||||
#define ACLK_TOP_ROOT 256
|
||||
#define PCLK_TOP_ROOT 257
|
||||
#define ACLK_LOW_TOP_ROOT 258
|
||||
#define PCLK_CRU 259
|
||||
#define PCLK_GPU_ROOT 260
|
||||
#define CLK_GPU_SRC 261
|
||||
#define CLK_GPU 262
|
||||
#define CLK_GPU_COREGROUP 263
|
||||
#define CLK_GPU_STACKS 264
|
||||
#define PCLK_GPU_PVTM 265
|
||||
#define CLK_GPU_PVTM 266
|
||||
#define CLK_CORE_GPU_PVTM 267
|
||||
#define PCLK_GPU_GRF 268
|
||||
#define ACLK_ISP1_ROOT 269
|
||||
#define HCLK_ISP1_ROOT 270
|
||||
#define CLK_ISP1_CORE 271
|
||||
#define CLK_ISP1_CORE_MARVIN 272
|
||||
#define CLK_ISP1_CORE_VICAP 273
|
||||
#define ACLK_ISP1 274
|
||||
#define HCLK_ISP1 275
|
||||
#define ACLK_NPU1 276
|
||||
#define HCLK_NPU1 277
|
||||
#define ACLK_NPU2 278
|
||||
#define HCLK_NPU2 279
|
||||
#define HCLK_NPU_CM0_ROOT 280
|
||||
#define FCLK_NPU_CM0_CORE 281
|
||||
#define CLK_NPU_CM0_RTC 282
|
||||
#define PCLK_NPU_PVTM 283
|
||||
#define PCLK_NPU_GRF 284
|
||||
#define CLK_NPU_PVTM 285
|
||||
#define CLK_CORE_NPU_PVTM 286
|
||||
#define ACLK_NPU0 287
|
||||
#define HCLK_NPU0 288
|
||||
#define HCLK_NPU_ROOT 289
|
||||
#define CLK_NPU_DSU0 290
|
||||
#define PCLK_NPU_ROOT 291
|
||||
#define PCLK_NPU_TIMER 292
|
||||
#define CLK_NPUTIMER_ROOT 293
|
||||
#define CLK_NPUTIMER0 294
|
||||
#define CLK_NPUTIMER1 295
|
||||
#define PCLK_NPU_WDT 296
|
||||
#define TCLK_NPU_WDT 297
|
||||
#define HCLK_EMMC 298
|
||||
#define ACLK_EMMC 299
|
||||
#define CCLK_EMMC 300
|
||||
#define BCLK_EMMC 301
|
||||
#define TMCLK_EMMC 302
|
||||
#define SCLK_SFC 303
|
||||
#define HCLK_SFC 304
|
||||
#define HCLK_SFC_XIP 305
|
||||
#define HCLK_NVM_ROOT 306
|
||||
#define ACLK_NVM_ROOT 307
|
||||
#define CLK_GMAC0_PTP_REF 308
|
||||
#define CLK_GMAC1_PTP_REF 309
|
||||
#define CLK_GMAC_125M 310
|
||||
#define CLK_GMAC_50M 311
|
||||
#define ACLK_PHP_GIC_ITS 312
|
||||
#define ACLK_MMU_PCIE 313
|
||||
#define ACLK_MMU_PHP 314
|
||||
#define ACLK_PCIE_4L_DBI 315
|
||||
#define ACLK_PCIE_2L_DBI 316
|
||||
#define ACLK_PCIE_1L0_DBI 317
|
||||
#define ACLK_PCIE_1L1_DBI 318
|
||||
#define ACLK_PCIE_1L2_DBI 319
|
||||
#define ACLK_PCIE_4L_MSTR 320
|
||||
#define ACLK_PCIE_2L_MSTR 321
|
||||
#define ACLK_PCIE_1L0_MSTR 322
|
||||
#define ACLK_PCIE_1L1_MSTR 323
|
||||
#define ACLK_PCIE_1L2_MSTR 324
|
||||
#define ACLK_PCIE_4L_SLV 325
|
||||
#define ACLK_PCIE_2L_SLV 326
|
||||
#define ACLK_PCIE_1L0_SLV 327
|
||||
#define ACLK_PCIE_1L1_SLV 328
|
||||
#define ACLK_PCIE_1L2_SLV 329
|
||||
#define PCLK_PCIE_4L 330
|
||||
#define PCLK_PCIE_2L 331
|
||||
#define PCLK_PCIE_1L0 332
|
||||
#define PCLK_PCIE_1L1 333
|
||||
#define PCLK_PCIE_1L2 334
|
||||
#define CLK_PCIE_AUX0 335
|
||||
#define CLK_PCIE_AUX1 336
|
||||
#define CLK_PCIE_AUX2 337
|
||||
#define CLK_PCIE_AUX3 338
|
||||
#define CLK_PCIE_AUX4 339
|
||||
#define CLK_PIPEPHY0_REF 340
|
||||
#define CLK_PIPEPHY1_REF 341
|
||||
#define CLK_PIPEPHY2_REF 342
|
||||
#define PCLK_PHP_ROOT 343
|
||||
#define PCLK_GMAC0 344
|
||||
#define PCLK_GMAC1 345
|
||||
#define ACLK_PCIE_ROOT 346
|
||||
#define ACLK_PHP_ROOT 347
|
||||
#define ACLK_PCIE_BRIDGE 348
|
||||
#define ACLK_GMAC0 349
|
||||
#define ACLK_GMAC1 350
|
||||
#define CLK_PMALIVE0 351
|
||||
#define CLK_PMALIVE1 352
|
||||
#define CLK_PMALIVE2 353
|
||||
#define ACLK_SATA0 354
|
||||
#define ACLK_SATA1 355
|
||||
#define ACLK_SATA2 356
|
||||
#define CLK_RXOOB0 357
|
||||
#define CLK_RXOOB1 358
|
||||
#define CLK_RXOOB2 359
|
||||
#define ACLK_USB3OTG2 360
|
||||
#define SUSPEND_CLK_USB3OTG2 361
|
||||
#define REF_CLK_USB3OTG2 362
|
||||
#define CLK_UTMI_OTG2 363
|
||||
#define CLK_PIPEPHY0_PIPE_G 364
|
||||
#define CLK_PIPEPHY1_PIPE_G 365
|
||||
#define CLK_PIPEPHY2_PIPE_G 366
|
||||
#define CLK_PIPEPHY0_PIPE_ASIC_G 367
|
||||
#define CLK_PIPEPHY1_PIPE_ASIC_G 368
|
||||
#define CLK_PIPEPHY2_PIPE_ASIC_G 369
|
||||
#define CLK_PIPEPHY2_PIPE_U3_G 370
|
||||
#define CLK_PCIE1L2_PIPE 371
|
||||
#define CLK_PCIE4L_PIPE 372
|
||||
#define CLK_PCIE2L_PIPE 373
|
||||
#define PCLK_PCIE_COMBO_PIPE_PHY0 374
|
||||
#define PCLK_PCIE_COMBO_PIPE_PHY1 375
|
||||
#define PCLK_PCIE_COMBO_PIPE_PHY2 376
|
||||
#define PCLK_PCIE_COMBO_PIPE_PHY 377
|
||||
#define HCLK_RGA3_1 378
|
||||
#define ACLK_RGA3_1 379
|
||||
#define CLK_RGA3_1_CORE 380
|
||||
#define ACLK_RGA3_ROOT 381
|
||||
#define HCLK_RGA3_ROOT 382
|
||||
#define ACLK_RKVDEC_CCU 383
|
||||
#define HCLK_RKVDEC0 384
|
||||
#define ACLK_RKVDEC0 385
|
||||
#define CLK_RKVDEC0_CA 386
|
||||
#define CLK_RKVDEC0_HEVC_CA 387
|
||||
#define CLK_RKVDEC0_CORE 388
|
||||
#define HCLK_RKVDEC1 389
|
||||
#define ACLK_RKVDEC1 390
|
||||
#define CLK_RKVDEC1_CA 391
|
||||
#define CLK_RKVDEC1_HEVC_CA 392
|
||||
#define CLK_RKVDEC1_CORE 393
|
||||
#define HCLK_SDIO 394
|
||||
#define CCLK_SRC_SDIO 395
|
||||
#define ACLK_USB_ROOT 396
|
||||
#define HCLK_USB_ROOT 397
|
||||
#define HCLK_HOST0 398
|
||||
#define HCLK_HOST_ARB0 399
|
||||
#define HCLK_HOST1 400
|
||||
#define HCLK_HOST_ARB1 401
|
||||
#define ACLK_USB3OTG0 402
|
||||
#define SUSPEND_CLK_USB3OTG0 403
|
||||
#define REF_CLK_USB3OTG0 404
|
||||
#define ACLK_USB3OTG1 405
|
||||
#define SUSPEND_CLK_USB3OTG1 406
|
||||
#define REF_CLK_USB3OTG1 407
|
||||
#define UTMI_OHCI_CLK48_HOST0 408
|
||||
#define UTMI_OHCI_CLK48_HOST1 409
|
||||
#define HCLK_IEP2P0 410
|
||||
#define ACLK_IEP2P0 411
|
||||
#define CLK_IEP2P0_CORE 412
|
||||
#define ACLK_JPEG_ENCODER0 413
|
||||
#define HCLK_JPEG_ENCODER0 414
|
||||
#define ACLK_JPEG_ENCODER1 415
|
||||
#define HCLK_JPEG_ENCODER1 416
|
||||
#define ACLK_JPEG_ENCODER2 417
|
||||
#define HCLK_JPEG_ENCODER2 418
|
||||
#define ACLK_JPEG_ENCODER3 419
|
||||
#define HCLK_JPEG_ENCODER3 420
|
||||
#define ACLK_JPEG_DECODER 421
|
||||
#define HCLK_JPEG_DECODER 422
|
||||
#define HCLK_RGA2 423
|
||||
#define ACLK_RGA2 424
|
||||
#define CLK_RGA2_CORE 425
|
||||
#define HCLK_RGA3_0 426
|
||||
#define ACLK_RGA3_0 427
|
||||
#define CLK_RGA3_0_CORE 428
|
||||
#define ACLK_VDPU_ROOT 429
|
||||
#define ACLK_VDPU_LOW_ROOT 430
|
||||
#define HCLK_VDPU_ROOT 431
|
||||
#define ACLK_JPEG_DECODER_ROOT 432
|
||||
#define ACLK_VPU 433
|
||||
#define HCLK_VPU 434
|
||||
#define HCLK_RKVENC0_ROOT 435
|
||||
#define ACLK_RKVENC0_ROOT 436
|
||||
#define HCLK_RKVENC0 437
|
||||
#define ACLK_RKVENC0 438
|
||||
#define CLK_RKVENC0_CORE 439
|
||||
#define HCLK_RKVENC1_ROOT 440
|
||||
#define ACLK_RKVENC1_ROOT 441
|
||||
#define HCLK_RKVENC1 442
|
||||
#define ACLK_RKVENC1 443
|
||||
#define CLK_RKVENC1_CORE 444
|
||||
#define ICLK_CSIHOST01 445
|
||||
#define ICLK_CSIHOST0 446
|
||||
#define ICLK_CSIHOST1 447
|
||||
#define PCLK_CSI_HOST_0 448
|
||||
#define PCLK_CSI_HOST_1 449
|
||||
#define PCLK_CSI_HOST_2 450
|
||||
#define PCLK_CSI_HOST_3 451
|
||||
#define PCLK_CSI_HOST_4 452
|
||||
#define PCLK_CSI_HOST_5 453
|
||||
#define ACLK_FISHEYE0 454
|
||||
#define HCLK_FISHEYE0 455
|
||||
#define CLK_FISHEYE0_CORE 456
|
||||
#define ACLK_FISHEYE1 457
|
||||
#define HCLK_FISHEYE1 458
|
||||
#define CLK_FISHEYE1_CORE 459
|
||||
#define CLK_ISP0_CORE 460
|
||||
#define CLK_ISP0_CORE_MARVIN 461
|
||||
#define CLK_ISP0_CORE_VICAP 462
|
||||
#define ACLK_ISP0 463
|
||||
#define HCLK_ISP0 464
|
||||
#define ACLK_VI_ROOT 465
|
||||
#define HCLK_VI_ROOT 466
|
||||
#define PCLK_VI_ROOT 467
|
||||
#define DCLK_VICAP 468
|
||||
#define ACLK_VICAP 469
|
||||
#define HCLK_VICAP 470
|
||||
#define PCLK_DP0 471
|
||||
#define PCLK_DP1 472
|
||||
#define PCLK_S_DP0 473
|
||||
#define PCLK_S_DP1 474
|
||||
#define CLK_DP0 475
|
||||
#define CLK_DP1 476
|
||||
#define HCLK_HDCP_KEY0 477
|
||||
#define ACLK_HDCP0 478
|
||||
#define HCLK_HDCP0 479
|
||||
#define PCLK_HDCP0 480
|
||||
#define HCLK_I2S4_8CH 481
|
||||
#define ACLK_TRNG0 482
|
||||
#define PCLK_TRNG0 483
|
||||
#define ACLK_VO0_ROOT 484
|
||||
#define HCLK_VO0_ROOT 485
|
||||
#define HCLK_VO0_S_ROOT 486
|
||||
#define PCLK_VO0_ROOT 487
|
||||
#define PCLK_VO0_S_ROOT 488
|
||||
#define PCLK_VO0GRF 489
|
||||
#define CLK_I2S4_8CH_TX_SRC 490
|
||||
#define CLK_I2S4_8CH_TX_FRAC 491
|
||||
#define MCLK_I2S4_8CH_TX 492
|
||||
#define CLK_I2S4_8CH_TX 493
|
||||
#define HCLK_I2S8_8CH 494
|
||||
#define CLK_I2S8_8CH_TX_SRC 495
|
||||
#define CLK_I2S8_8CH_TX_FRAC 496
|
||||
#define MCLK_I2S8_8CH_TX 497
|
||||
#define CLK_I2S8_8CH_TX 498
|
||||
#define HCLK_SPDIF2_DP0 499
|
||||
#define CLK_SPDIF2_DP0_SRC 500
|
||||
#define CLK_SPDIF2_DP0_FRAC 501
|
||||
#define MCLK_SPDIF2_DP0 502
|
||||
#define CLK_SPDIF2_DP0 503
|
||||
#define MCLK_SPDIF2 504
|
||||
#define HCLK_SPDIF5_DP1 505
|
||||
#define CLK_SPDIF5_DP1_SRC 506
|
||||
#define CLK_SPDIF5_DP1_FRAC 507
|
||||
#define MCLK_SPDIF5_DP1 508
|
||||
#define CLK_SPDIF5_DP1 509
|
||||
#define MCLK_SPDIF5 510
|
||||
#define PCLK_EDP0 511
|
||||
#define CLK_EDP0_24M 512
|
||||
#define CLK_EDP0_200M 513
|
||||
#define PCLK_EDP1 514
|
||||
#define CLK_EDP1_24M 515
|
||||
#define CLK_EDP1_200M 516
|
||||
#define HCLK_HDCP_KEY1 517
|
||||
#define ACLK_HDCP1 518
|
||||
#define HCLK_HDCP1 519
|
||||
#define PCLK_HDCP1 520
|
||||
#define ACLK_HDMIRX 521
|
||||
#define PCLK_HDMIRX 522
|
||||
#define CLK_HDMIRX_REF 523
|
||||
#define CLK_HDMIRX_AUD_SRC 524
|
||||
#define CLK_HDMIRX_AUD_FRAC 525
|
||||
#define CLK_HDMIRX_AUD 526
|
||||
#define CLK_HDMIRX_AUD_P_MUX 527
|
||||
#define PCLK_HDMITX0 528
|
||||
#define CLK_HDMITX0_EARC 529
|
||||
#define CLK_HDMITX0_REF 530
|
||||
#define PCLK_HDMITX1 531
|
||||
#define CLK_HDMITX1_EARC 532
|
||||
#define CLK_HDMITX1_REF 533
|
||||
#define CLK_HDMITRX_REFSRC 534
|
||||
#define ACLK_TRNG1 535
|
||||
#define PCLK_TRNG1 536
|
||||
#define ACLK_HDCP1_ROOT 537
|
||||
#define ACLK_HDMIRX_ROOT 538
|
||||
#define HCLK_VO1_ROOT 539
|
||||
#define HCLK_VO1_S_ROOT 540
|
||||
#define PCLK_VO1_ROOT 541
|
||||
#define PCLK_VO1_S_ROOT 542
|
||||
#define PCLK_S_EDP0 543
|
||||
#define PCLK_S_EDP1 544
|
||||
#define PCLK_S_HDMIRX 545
|
||||
#define HCLK_I2S10_8CH 546
|
||||
#define CLK_I2S10_8CH_RX_SRC 547
|
||||
#define CLK_I2S10_8CH_RX_FRAC 548
|
||||
#define CLK_I2S10_8CH_RX 549
|
||||
#define MCLK_I2S10_8CH_RX 550
|
||||
#define HCLK_I2S7_8CH 551
|
||||
#define CLK_I2S7_8CH_RX_SRC 552
|
||||
#define CLK_I2S7_8CH_RX_FRAC 553
|
||||
#define CLK_I2S7_8CH_RX 554
|
||||
#define MCLK_I2S7_8CH_RX 555
|
||||
#define HCLK_I2S9_8CH 556
|
||||
#define CLK_I2S9_8CH_RX_SRC 557
|
||||
#define CLK_I2S9_8CH_RX_FRAC 558
|
||||
#define CLK_I2S9_8CH_RX 559
|
||||
#define MCLK_I2S9_8CH_RX 560
|
||||
#define CLK_I2S5_8CH_TX_SRC 561
|
||||
#define CLK_I2S5_8CH_TX_FRAC 562
|
||||
#define CLK_I2S5_8CH_TX 563
|
||||
#define MCLK_I2S5_8CH_TX 564
|
||||
#define HCLK_I2S5_8CH 565
|
||||
#define CLK_I2S6_8CH_TX_SRC 566
|
||||
#define CLK_I2S6_8CH_TX_FRAC 567
|
||||
#define CLK_I2S6_8CH_TX 568
|
||||
#define MCLK_I2S6_8CH_TX 569
|
||||
#define CLK_I2S6_8CH_RX_SRC 570
|
||||
#define CLK_I2S6_8CH_RX_FRAC 571
|
||||
#define CLK_I2S6_8CH_RX 572
|
||||
#define MCLK_I2S6_8CH_RX 573
|
||||
#define I2S6_8CH_MCLKOUT 574
|
||||
#define HCLK_I2S6_8CH 575
|
||||
#define HCLK_SPDIF3 576
|
||||
#define CLK_SPDIF3_SRC 577
|
||||
#define CLK_SPDIF3_FRAC 578
|
||||
#define CLK_SPDIF3 579
|
||||
#define MCLK_SPDIF3 580
|
||||
#define HCLK_SPDIF4 581
|
||||
#define CLK_SPDIF4_SRC 582
|
||||
#define CLK_SPDIF4_FRAC 583
|
||||
#define CLK_SPDIF4 584
|
||||
#define MCLK_SPDIF4 585
|
||||
#define HCLK_SPDIFRX0 586
|
||||
#define MCLK_SPDIFRX0 587
|
||||
#define HCLK_SPDIFRX1 588
|
||||
#define MCLK_SPDIFRX1 589
|
||||
#define HCLK_SPDIFRX2 590
|
||||
#define MCLK_SPDIFRX2 591
|
||||
#define ACLK_VO1USB_TOP_ROOT 592
|
||||
#define HCLK_VO1USB_TOP_ROOT 593
|
||||
#define CLK_HDMIHDP0 594
|
||||
#define CLK_HDMIHDP1 595
|
||||
#define PCLK_HDPTX0 596
|
||||
#define PCLK_HDPTX1 597
|
||||
#define PCLK_USBDPPHY0 598
|
||||
#define PCLK_USBDPPHY1 599
|
||||
#define ACLK_VOP_ROOT 600
|
||||
#define ACLK_VOP_LOW_ROOT 601
|
||||
#define HCLK_VOP_ROOT 602
|
||||
#define PCLK_VOP_ROOT 603
|
||||
#define HCLK_VOP 604
|
||||
#define ACLK_VOP 605
|
||||
#define DCLK_VOP0_SRC 606
|
||||
#define DCLK_VOP1_SRC 607
|
||||
#define DCLK_VOP2_SRC 608
|
||||
#define DCLK_VOP0 609
|
||||
#define DCLK_VOP1 610
|
||||
#define DCLK_VOP2 611
|
||||
#define DCLK_VOP3 612
|
||||
#define PCLK_DSIHOST0 613
|
||||
#define PCLK_DSIHOST1 614
|
||||
#define CLK_DSIHOST0 615
|
||||
#define CLK_DSIHOST1 616
|
||||
#define CLK_VOP_PMU 617
|
||||
#define ACLK_VOP_DOBY 618
|
||||
#define ACLK_VOP_SUB_SRC 619
|
||||
#define CLK_USBDP_PHY0_IMMORTAL 620
|
||||
#define CLK_USBDP_PHY1_IMMORTAL 621
|
||||
#define CLK_PMU0 622
|
||||
#define PCLK_PMU0 623
|
||||
#define PCLK_PMU0IOC 624
|
||||
#define PCLK_GPIO0 625
|
||||
#define DBCLK_GPIO0 626
|
||||
#define PCLK_I2C0 627
|
||||
#define CLK_I2C0 628
|
||||
#define HCLK_I2S1_8CH 629
|
||||
#define CLK_I2S1_8CH_TX_SRC 630
|
||||
#define CLK_I2S1_8CH_TX_FRAC 631
|
||||
#define CLK_I2S1_8CH_TX 632
|
||||
#define MCLK_I2S1_8CH_TX 633
|
||||
#define CLK_I2S1_8CH_RX_SRC 634
|
||||
#define CLK_I2S1_8CH_RX_FRAC 635
|
||||
#define CLK_I2S1_8CH_RX 636
|
||||
#define MCLK_I2S1_8CH_RX 637
|
||||
#define I2S1_8CH_MCLKOUT 638
|
||||
#define CLK_PMU1_50M_SRC 639
|
||||
#define CLK_PMU1_100M_SRC 640
|
||||
#define CLK_PMU1_200M_SRC 641
|
||||
#define CLK_PMU1_300M_SRC 642
|
||||
#define CLK_PMU1_400M_SRC 643
|
||||
#define HCLK_PMU1_ROOT 644
|
||||
#define PCLK_PMU1_ROOT 645
|
||||
#define PCLK_PMU0_ROOT 646
|
||||
#define HCLK_PMU_CM0_ROOT 647
|
||||
#define PCLK_PMU1 648
|
||||
#define CLK_DDR_FAIL_SAFE 649
|
||||
#define CLK_PMU1 650
|
||||
#define HCLK_PDM0 651
|
||||
#define MCLK_PDM0 652
|
||||
#define HCLK_VAD 653
|
||||
#define FCLK_PMU_CM0_CORE 654
|
||||
#define CLK_PMU_CM0_RTC 655
|
||||
#define PCLK_PMU1_IOC 656
|
||||
#define PCLK_PMU1PWM 657
|
||||
#define CLK_PMU1PWM 658
|
||||
#define CLK_PMU1PWM_CAPTURE 659
|
||||
#define PCLK_PMU1TIMER 660
|
||||
#define CLK_PMU1TIMER_ROOT 661
|
||||
#define CLK_PMU1TIMER0 662
|
||||
#define CLK_PMU1TIMER1 663
|
||||
#define CLK_UART0_SRC 664
|
||||
#define CLK_UART0_FRAC 665
|
||||
#define CLK_UART0 666
|
||||
#define SCLK_UART0 667
|
||||
#define PCLK_UART0 668
|
||||
#define PCLK_PMU1WDT 669
|
||||
#define TCLK_PMU1WDT 670
|
||||
#define CLK_CR_PARA 671
|
||||
#define CLK_USB2PHY_HDPTXRXPHY_REF 672
|
||||
#define CLK_USBDPPHY_MIPIDCPPHY_REF 673
|
||||
#define CLK_REF_PIPE_PHY0_OSC_SRC 674
|
||||
#define CLK_REF_PIPE_PHY1_OSC_SRC 675
|
||||
#define CLK_REF_PIPE_PHY2_OSC_SRC 676
|
||||
#define CLK_REF_PIPE_PHY0_PLL_SRC 677
|
||||
#define CLK_REF_PIPE_PHY1_PLL_SRC 678
|
||||
#define CLK_REF_PIPE_PHY2_PLL_SRC 679
|
||||
#define CLK_REF_PIPE_PHY0 680
|
||||
#define CLK_REF_PIPE_PHY1 681
|
||||
#define CLK_REF_PIPE_PHY2 682
|
||||
#define SCLK_SDIO_DRV 683
|
||||
#define SCLK_SDIO_SAMPLE 684
|
||||
#define SCLK_SDMMC_DRV 685
|
||||
#define SCLK_SDMMC_SAMPLE 686
|
||||
#define CLK_PCIE1L0_PIPE 687
|
||||
#define CLK_PCIE1L1_PIPE 688
|
||||
#define CLK_BIGCORE0_PVTM 689
|
||||
#define CLK_CORE_BIGCORE0_PVTM 690
|
||||
#define CLK_BIGCORE1_PVTM 691
|
||||
#define CLK_CORE_BIGCORE1_PVTM 692
|
||||
#define CLK_LITCORE_PVTM 693
|
||||
#define CLK_CORE_LITCORE_PVTM 694
|
||||
#define CLK_AUX16M_0 695
|
||||
#define CLK_AUX16M_1 696
|
||||
#define CLK_PHY0_REF_ALT_P 697
|
||||
#define CLK_PHY0_REF_ALT_M 698
|
||||
#define CLK_PHY1_REF_ALT_P 699
|
||||
#define CLK_PHY1_REF_ALT_M 700
|
||||
#define ACLK_ISP1_PRE 701
|
||||
#define HCLK_ISP1_PRE 702
|
||||
#define HCLK_NVM 703
|
||||
#define ACLK_USB 704
|
||||
#define HCLK_USB 705
|
||||
#define ACLK_JPEG_DECODER_PRE 706
|
||||
#define ACLK_VDPU_LOW_PRE 707
|
||||
#define ACLK_RKVENC1_PRE 708
|
||||
#define HCLK_RKVENC1_PRE 709
|
||||
#define HCLK_RKVDEC0_PRE 710
|
||||
#define ACLK_RKVDEC0_PRE 711
|
||||
#define HCLK_RKVDEC1_PRE 712
|
||||
#define ACLK_RKVDEC1_PRE 713
|
||||
#define ACLK_HDCP0_PRE 714
|
||||
#define HCLK_VO0 715
|
||||
#define ACLK_HDCP1_PRE 716
|
||||
#define HCLK_VO1 717
|
||||
#define ACLK_AV1_PRE 718
|
||||
#define PCLK_AV1_PRE 719
|
||||
#define HCLK_SDIO_PRE 720
|
||||
#define PCLK_VO1GRF 721
|
||||
|
||||
/* scmi-clocks indices */
|
||||
|
||||
#define SCMI_CLK_CPUL 0
|
||||
#define SCMI_CLK_DSU 1
|
||||
#define SCMI_CLK_CPUB01 2
|
||||
#define SCMI_CLK_CPUB23 3
|
||||
#define SCMI_CLK_DDR 4
|
||||
#define SCMI_CLK_GPU 5
|
||||
#define SCMI_CLK_NPU 6
|
||||
#define SCMI_CLK_SBUS 7
|
||||
#define SCMI_PCLK_SBUS 8
|
||||
#define SCMI_CCLK_SD 9
|
||||
#define SCMI_DCLK_SD 10
|
||||
#define SCMI_ACLK_SECURE_NS 11
|
||||
#define SCMI_HCLK_SECURE_NS 12
|
||||
#define SCMI_TCLK_WDT 13
|
||||
#define SCMI_KEYLADDER_CORE 14
|
||||
#define SCMI_KEYLADDER_RNG 15
|
||||
#define SCMI_ACLK_SECURE_S 16
|
||||
#define SCMI_HCLK_SECURE_S 17
|
||||
#define SCMI_PCLK_SECURE_S 18
|
||||
#define SCMI_CRYPTO_RNG 19
|
||||
#define SCMI_CRYPTO_CORE 20
|
||||
#define SCMI_CRYPTO_PKA 21
|
||||
#define SCMI_SPLL 22
|
||||
#define SCMI_HCLK_SD 23
|
||||
|
||||
#endif
|
||||
@@ -1,69 +0,0 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
|
||||
#ifndef __DT_BINDINGS_POWER_RK3588_POWER_H__
|
||||
#define __DT_BINDINGS_POWER_RK3588_POWER_H__
|
||||
|
||||
/* VD_LITDSU */
|
||||
#define RK3588_PD_CPU_0 0
|
||||
#define RK3588_PD_CPU_1 1
|
||||
#define RK3588_PD_CPU_2 2
|
||||
#define RK3588_PD_CPU_3 3
|
||||
|
||||
/* VD_BIGCORE0 */
|
||||
#define RK3588_PD_CPU_4 4
|
||||
#define RK3588_PD_CPU_5 5
|
||||
|
||||
/* VD_BIGCORE1 */
|
||||
#define RK3588_PD_CPU_6 6
|
||||
#define RK3588_PD_CPU_7 7
|
||||
|
||||
/* VD_NPU */
|
||||
#define RK3588_PD_NPU 8
|
||||
#define RK3588_PD_NPUTOP 9
|
||||
#define RK3588_PD_NPU1 10
|
||||
#define RK3588_PD_NPU2 11
|
||||
|
||||
/* VD_GPU */
|
||||
#define RK3588_PD_GPU 12
|
||||
|
||||
/* VD_VCODEC */
|
||||
#define RK3588_PD_VCODEC 13
|
||||
#define RK3588_PD_RKVDEC0 14
|
||||
#define RK3588_PD_RKVDEC1 15
|
||||
#define RK3588_PD_VENC0 16
|
||||
#define RK3588_PD_VENC1 17
|
||||
|
||||
/* VD_DD01 */
|
||||
#define RK3588_PD_DDR01 18
|
||||
|
||||
/* VD_DD23 */
|
||||
#define RK3588_PD_DDR23 19
|
||||
|
||||
/* VD_LOGIC */
|
||||
#define RK3588_PD_CENTER 20
|
||||
#define RK3588_PD_VDPU 21
|
||||
#define RK3588_PD_RGA30 22
|
||||
#define RK3588_PD_AV1 23
|
||||
#define RK3588_PD_VOP 24
|
||||
#define RK3588_PD_VO0 25
|
||||
#define RK3588_PD_VO1 26
|
||||
#define RK3588_PD_VI 27
|
||||
#define RK3588_PD_ISP1 28
|
||||
#define RK3588_PD_FEC 29
|
||||
#define RK3588_PD_RGA31 30
|
||||
#define RK3588_PD_USB 31
|
||||
#define RK3588_PD_PHP 32
|
||||
#define RK3588_PD_GMAC 33
|
||||
#define RK3588_PD_PCIE 34
|
||||
#define RK3588_PD_NVM 35
|
||||
#define RK3588_PD_NVM0 36
|
||||
#define RK3588_PD_SDIO 37
|
||||
#define RK3588_PD_AUDIO 38
|
||||
#define RK3588_PD_SECURE 39
|
||||
#define RK3588_PD_SDMMC 40
|
||||
#define RK3588_PD_CRYPTO 41
|
||||
#define RK3588_PD_BUS 42
|
||||
|
||||
/* VD_PMU */
|
||||
#define RK3588_PD_PMU1 43
|
||||
|
||||
#endif
|
||||
-756
@@ -1,756 +0,0 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
|
||||
* Copyright (c) 2022 Collabora Ltd.
|
||||
*
|
||||
* Author: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
* Author: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H
|
||||
#define _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H
|
||||
|
||||
#define SRST_A_TOP_BIU 0
|
||||
#define SRST_P_TOP_BIU 1
|
||||
#define SRST_P_CSIPHY0 2
|
||||
#define SRST_CSIPHY0 3
|
||||
#define SRST_P_CSIPHY1 4
|
||||
#define SRST_CSIPHY1 5
|
||||
#define SRST_A_TOP_M500_BIU 6
|
||||
|
||||
#define SRST_A_TOP_M400_BIU 7
|
||||
#define SRST_A_TOP_S200_BIU 8
|
||||
#define SRST_A_TOP_S400_BIU 9
|
||||
#define SRST_A_TOP_M300_BIU 10
|
||||
#define SRST_USBDP_COMBO_PHY0_INIT 11
|
||||
#define SRST_USBDP_COMBO_PHY0_CMN 12
|
||||
#define SRST_USBDP_COMBO_PHY0_LANE 13
|
||||
#define SRST_USBDP_COMBO_PHY0_PCS 14
|
||||
#define SRST_USBDP_COMBO_PHY1_INIT 15
|
||||
|
||||
#define SRST_USBDP_COMBO_PHY1_CMN 16
|
||||
#define SRST_USBDP_COMBO_PHY1_LANE 17
|
||||
#define SRST_USBDP_COMBO_PHY1_PCS 18
|
||||
#define SRST_DCPHY0 19
|
||||
#define SRST_P_MIPI_DCPHY0 20
|
||||
#define SRST_P_MIPI_DCPHY0_GRF 21
|
||||
|
||||
#define SRST_DCPHY1 22
|
||||
#define SRST_P_MIPI_DCPHY1 23
|
||||
#define SRST_P_MIPI_DCPHY1_GRF 24
|
||||
#define SRST_P_APB2ASB_SLV_CDPHY 25
|
||||
#define SRST_P_APB2ASB_SLV_CSIPHY 26
|
||||
#define SRST_P_APB2ASB_SLV_VCCIO3_5 27
|
||||
#define SRST_P_APB2ASB_SLV_VCCIO6 28
|
||||
#define SRST_P_APB2ASB_SLV_EMMCIO 29
|
||||
#define SRST_P_APB2ASB_SLV_IOC_TOP 30
|
||||
#define SRST_P_APB2ASB_SLV_IOC_RIGHT 31
|
||||
|
||||
#define SRST_P_CRU 32
|
||||
#define SRST_A_CHANNEL_SECURE2VO1USB 33
|
||||
#define SRST_A_CHANNEL_SECURE2CENTER 34
|
||||
#define SRST_H_CHANNEL_SECURE2VO1USB 35
|
||||
#define SRST_H_CHANNEL_SECURE2CENTER 36
|
||||
|
||||
#define SRST_P_CHANNEL_SECURE2VO1USB 37
|
||||
#define SRST_P_CHANNEL_SECURE2CENTER 38
|
||||
|
||||
#define SRST_H_AUDIO_BIU 39
|
||||
#define SRST_P_AUDIO_BIU 40
|
||||
#define SRST_H_I2S0_8CH 41
|
||||
#define SRST_M_I2S0_8CH_TX 42
|
||||
#define SRST_M_I2S0_8CH_RX 43
|
||||
#define SRST_P_ACDCDIG 44
|
||||
#define SRST_H_I2S2_2CH 45
|
||||
#define SRST_H_I2S3_2CH 46
|
||||
|
||||
#define SRST_M_I2S2_2CH 47
|
||||
#define SRST_M_I2S3_2CH 48
|
||||
#define SRST_DAC_ACDCDIG 49
|
||||
#define SRST_H_SPDIF0 50
|
||||
|
||||
#define SRST_M_SPDIF0 51
|
||||
#define SRST_H_SPDIF1 52
|
||||
#define SRST_M_SPDIF1 53
|
||||
#define SRST_H_PDM1 54
|
||||
#define SRST_PDM1 55
|
||||
|
||||
#define SRST_A_BUS_BIU 56
|
||||
#define SRST_P_BUS_BIU 57
|
||||
#define SRST_A_GIC 58
|
||||
#define SRST_A_GIC_DBG 59
|
||||
#define SRST_A_DMAC0 60
|
||||
#define SRST_A_DMAC1 61
|
||||
#define SRST_A_DMAC2 62
|
||||
#define SRST_P_I2C1 63
|
||||
#define SRST_P_I2C2 64
|
||||
#define SRST_P_I2C3 65
|
||||
#define SRST_P_I2C4 66
|
||||
#define SRST_P_I2C5 67
|
||||
#define SRST_P_I2C6 68
|
||||
#define SRST_P_I2C7 69
|
||||
#define SRST_P_I2C8 70
|
||||
|
||||
#define SRST_I2C1 71
|
||||
#define SRST_I2C2 72
|
||||
#define SRST_I2C3 73
|
||||
#define SRST_I2C4 74
|
||||
#define SRST_I2C5 75
|
||||
#define SRST_I2C6 76
|
||||
#define SRST_I2C7 77
|
||||
#define SRST_I2C8 78
|
||||
#define SRST_P_CAN0 79
|
||||
#define SRST_CAN0 80
|
||||
#define SRST_P_CAN1 81
|
||||
#define SRST_CAN1 82
|
||||
#define SRST_P_CAN2 83
|
||||
#define SRST_CAN2 84
|
||||
#define SRST_P_SARADC 85
|
||||
|
||||
#define SRST_P_TSADC 86
|
||||
#define SRST_TSADC 87
|
||||
#define SRST_P_UART1 88
|
||||
#define SRST_P_UART2 89
|
||||
#define SRST_P_UART3 90
|
||||
#define SRST_P_UART4 91
|
||||
#define SRST_P_UART5 92
|
||||
#define SRST_P_UART6 93
|
||||
#define SRST_P_UART7 94
|
||||
#define SRST_P_UART8 95
|
||||
#define SRST_P_UART9 96
|
||||
#define SRST_S_UART1 97
|
||||
|
||||
#define SRST_S_UART2 98
|
||||
#define SRST_S_UART3 99
|
||||
#define SRST_S_UART4 100
|
||||
#define SRST_S_UART5 101
|
||||
#define SRST_S_UART6 102
|
||||
#define SRST_S_UART7 103
|
||||
|
||||
#define SRST_S_UART8 104
|
||||
#define SRST_S_UART9 105
|
||||
#define SRST_P_SPI0 106
|
||||
#define SRST_P_SPI1 107
|
||||
#define SRST_P_SPI2 108
|
||||
#define SRST_P_SPI3 109
|
||||
#define SRST_P_SPI4 110
|
||||
#define SRST_SPI0 111
|
||||
#define SRST_SPI1 112
|
||||
#define SRST_SPI2 113
|
||||
#define SRST_SPI3 114
|
||||
#define SRST_SPI4 115
|
||||
|
||||
#define SRST_P_WDT0 116
|
||||
#define SRST_T_WDT0 117
|
||||
#define SRST_P_SYS_GRF 118
|
||||
#define SRST_P_PWM1 119
|
||||
#define SRST_PWM1 120
|
||||
#define SRST_P_PWM2 121
|
||||
#define SRST_PWM2 122
|
||||
#define SRST_P_PWM3 123
|
||||
#define SRST_PWM3 124
|
||||
#define SRST_P_BUSTIMER0 125
|
||||
#define SRST_P_BUSTIMER1 126
|
||||
#define SRST_BUSTIMER0 127
|
||||
|
||||
#define SRST_BUSTIMER1 128
|
||||
#define SRST_BUSTIMER2 129
|
||||
#define SRST_BUSTIMER3 130
|
||||
#define SRST_BUSTIMER4 131
|
||||
#define SRST_BUSTIMER5 132
|
||||
#define SRST_BUSTIMER6 133
|
||||
#define SRST_BUSTIMER7 134
|
||||
#define SRST_BUSTIMER8 135
|
||||
#define SRST_BUSTIMER9 136
|
||||
#define SRST_BUSTIMER10 137
|
||||
#define SRST_BUSTIMER11 138
|
||||
#define SRST_P_MAILBOX0 139
|
||||
#define SRST_P_MAILBOX1 140
|
||||
#define SRST_P_MAILBOX2 141
|
||||
#define SRST_P_GPIO1 142
|
||||
#define SRST_GPIO1 143
|
||||
|
||||
#define SRST_P_GPIO2 144
|
||||
#define SRST_GPIO2 145
|
||||
#define SRST_P_GPIO3 146
|
||||
#define SRST_GPIO3 147
|
||||
#define SRST_P_GPIO4 148
|
||||
#define SRST_GPIO4 149
|
||||
#define SRST_A_DECOM 150
|
||||
#define SRST_P_DECOM 151
|
||||
#define SRST_D_DECOM 152
|
||||
#define SRST_P_TOP 153
|
||||
#define SRST_A_GICADB_GIC2CORE_BUS 154
|
||||
#define SRST_P_DFT2APB 155
|
||||
#define SRST_P_APB2ASB_MST_TOP 156
|
||||
#define SRST_P_APB2ASB_MST_CDPHY 157
|
||||
#define SRST_P_APB2ASB_MST_BOT_RIGHT 158
|
||||
|
||||
#define SRST_P_APB2ASB_MST_IOC_TOP 159
|
||||
#define SRST_P_APB2ASB_MST_IOC_RIGHT 160
|
||||
#define SRST_P_APB2ASB_MST_CSIPHY 161
|
||||
#define SRST_P_APB2ASB_MST_VCCIO3_5 162
|
||||
#define SRST_P_APB2ASB_MST_VCCIO6 163
|
||||
#define SRST_P_APB2ASB_MST_EMMCIO 164
|
||||
#define SRST_A_SPINLOCK 165
|
||||
#define SRST_P_OTPC_NS 166
|
||||
#define SRST_OTPC_NS 167
|
||||
#define SRST_OTPC_ARB 168
|
||||
|
||||
#define SRST_P_BUSIOC 169
|
||||
#define SRST_P_PMUCM0_INTMUX 170
|
||||
#define SRST_P_DDRCM0_INTMUX 171
|
||||
|
||||
#define SRST_P_DDR_DFICTL_CH0 172
|
||||
#define SRST_P_DDR_MON_CH0 173
|
||||
#define SRST_P_DDR_STANDBY_CH0 174
|
||||
#define SRST_P_DDR_UPCTL_CH0 175
|
||||
#define SRST_TM_DDR_MON_CH0 176
|
||||
#define SRST_P_DDR_GRF_CH01 177
|
||||
#define SRST_DFI_CH0 178
|
||||
#define SRST_SBR_CH0 179
|
||||
#define SRST_DDR_UPCTL_CH0 180
|
||||
#define SRST_DDR_DFICTL_CH0 181
|
||||
#define SRST_DDR_MON_CH0 182
|
||||
#define SRST_DDR_STANDBY_CH0 183
|
||||
#define SRST_A_DDR_UPCTL_CH0 184
|
||||
#define SRST_P_DDR_DFICTL_CH1 185
|
||||
#define SRST_P_DDR_MON_CH1 186
|
||||
#define SRST_P_DDR_STANDBY_CH1 187
|
||||
|
||||
#define SRST_P_DDR_UPCTL_CH1 188
|
||||
#define SRST_TM_DDR_MON_CH1 189
|
||||
#define SRST_DFI_CH1 190
|
||||
#define SRST_SBR_CH1 191
|
||||
#define SRST_DDR_UPCTL_CH1 192
|
||||
#define SRST_DDR_DFICTL_CH1 193
|
||||
#define SRST_DDR_MON_CH1 194
|
||||
#define SRST_DDR_STANDBY_CH1 195
|
||||
#define SRST_A_DDR_UPCTL_CH1 196
|
||||
#define SRST_A_DDR01_MSCH0 197
|
||||
#define SRST_A_DDR01_RS_MSCH0 198
|
||||
#define SRST_A_DDR01_FRS_MSCH0 199
|
||||
|
||||
#define SRST_A_DDR01_SCRAMBLE0 200
|
||||
#define SRST_A_DDR01_FRS_SCRAMBLE0 201
|
||||
#define SRST_A_DDR01_MSCH1 202
|
||||
#define SRST_A_DDR01_RS_MSCH1 203
|
||||
#define SRST_A_DDR01_FRS_MSCH1 204
|
||||
#define SRST_A_DDR01_SCRAMBLE1 205
|
||||
#define SRST_A_DDR01_FRS_SCRAMBLE1 206
|
||||
#define SRST_P_DDR01_MSCH0 207
|
||||
#define SRST_P_DDR01_MSCH1 208
|
||||
|
||||
#define SRST_P_DDR_DFICTL_CH2 209
|
||||
#define SRST_P_DDR_MON_CH2 210
|
||||
#define SRST_P_DDR_STANDBY_CH2 211
|
||||
#define SRST_P_DDR_UPCTL_CH2 212
|
||||
#define SRST_TM_DDR_MON_CH2 213
|
||||
#define SRST_P_DDR_GRF_CH23 214
|
||||
#define SRST_DFI_CH2 215
|
||||
#define SRST_SBR_CH2 216
|
||||
#define SRST_DDR_UPCTL_CH2 217
|
||||
#define SRST_DDR_DFICTL_CH2 218
|
||||
#define SRST_DDR_MON_CH2 219
|
||||
#define SRST_DDR_STANDBY_CH2 220
|
||||
#define SRST_A_DDR_UPCTL_CH2 221
|
||||
#define SRST_P_DDR_DFICTL_CH3 222
|
||||
#define SRST_P_DDR_MON_CH3 223
|
||||
#define SRST_P_DDR_STANDBY_CH3 224
|
||||
|
||||
#define SRST_P_DDR_UPCTL_CH3 225
|
||||
#define SRST_TM_DDR_MON_CH3 226
|
||||
#define SRST_DFI_CH3 227
|
||||
#define SRST_SBR_CH3 228
|
||||
#define SRST_DDR_UPCTL_CH3 229
|
||||
#define SRST_DDR_DFICTL_CH3 230
|
||||
#define SRST_DDR_MON_CH3 231
|
||||
#define SRST_DDR_STANDBY_CH3 232
|
||||
#define SRST_A_DDR_UPCTL_CH3 233
|
||||
#define SRST_A_DDR23_MSCH2 234
|
||||
#define SRST_A_DDR23_RS_MSCH2 235
|
||||
#define SRST_A_DDR23_FRS_MSCH2 236
|
||||
|
||||
#define SRST_A_DDR23_SCRAMBLE2 237
|
||||
#define SRST_A_DDR23_FRS_SCRAMBLE2 238
|
||||
#define SRST_A_DDR23_MSCH3 239
|
||||
#define SRST_A_DDR23_RS_MSCH3 240
|
||||
#define SRST_A_DDR23_FRS_MSCH3 241
|
||||
#define SRST_A_DDR23_SCRAMBLE3 242
|
||||
#define SRST_A_DDR23_FRS_SCRAMBLE3 243
|
||||
#define SRST_P_DDR23_MSCH2 244
|
||||
#define SRST_P_DDR23_MSCH3 245
|
||||
|
||||
#define SRST_ISP1 246
|
||||
#define SRST_ISP1_VICAP 247
|
||||
#define SRST_A_ISP1_BIU 248
|
||||
#define SRST_H_ISP1_BIU 249
|
||||
|
||||
#define SRST_A_RKNN1 250
|
||||
#define SRST_A_RKNN1_BIU 251
|
||||
#define SRST_H_RKNN1 252
|
||||
#define SRST_H_RKNN1_BIU 253
|
||||
|
||||
#define SRST_A_RKNN2 254
|
||||
#define SRST_A_RKNN2_BIU 255
|
||||
#define SRST_H_RKNN2 256
|
||||
#define SRST_H_RKNN2_BIU 257
|
||||
|
||||
#define SRST_A_RKNN_DSU0 258
|
||||
#define SRST_P_NPUTOP_BIU 259
|
||||
#define SRST_P_NPU_TIMER 260
|
||||
#define SRST_NPUTIMER0 261
|
||||
#define SRST_NPUTIMER1 262
|
||||
#define SRST_P_NPU_WDT 263
|
||||
#define SRST_T_NPU_WDT 264
|
||||
#define SRST_P_NPU_PVTM 265
|
||||
#define SRST_P_NPU_GRF 266
|
||||
#define SRST_NPU_PVTM 267
|
||||
|
||||
#define SRST_NPU_PVTPLL 268
|
||||
#define SRST_H_NPU_CM0_BIU 269
|
||||
#define SRST_F_NPU_CM0_CORE 270
|
||||
#define SRST_T_NPU_CM0_JTAG 271
|
||||
#define SRST_A_RKNN0 272
|
||||
#define SRST_A_RKNN0_BIU 273
|
||||
#define SRST_H_RKNN0 274
|
||||
#define SRST_H_RKNN0_BIU 275
|
||||
|
||||
#define SRST_H_NVM_BIU 276
|
||||
#define SRST_A_NVM_BIU 277
|
||||
#define SRST_H_EMMC 278
|
||||
#define SRST_A_EMMC 279
|
||||
#define SRST_C_EMMC 280
|
||||
#define SRST_B_EMMC 281
|
||||
#define SRST_T_EMMC 282
|
||||
#define SRST_S_SFC 283
|
||||
#define SRST_H_SFC 284
|
||||
#define SRST_H_SFC_XIP 285
|
||||
|
||||
#define SRST_P_GRF 286
|
||||
#define SRST_P_DEC_BIU 287
|
||||
#define SRST_P_PHP_BIU 288
|
||||
#define SRST_A_PCIE_GRIDGE 289
|
||||
#define SRST_A_PHP_BIU 290
|
||||
#define SRST_A_GMAC0 291
|
||||
#define SRST_A_GMAC1 292
|
||||
#define SRST_A_PCIE_BIU 293
|
||||
#define SRST_PCIE0_POWER_UP 294
|
||||
#define SRST_PCIE1_POWER_UP 295
|
||||
#define SRST_PCIE2_POWER_UP 296
|
||||
|
||||
#define SRST_PCIE3_POWER_UP 297
|
||||
#define SRST_PCIE4_POWER_UP 298
|
||||
#define SRST_P_PCIE0 299
|
||||
#define SRST_P_PCIE1 300
|
||||
#define SRST_P_PCIE2 301
|
||||
#define SRST_P_PCIE3 302
|
||||
|
||||
#define SRST_P_PCIE4 303
|
||||
#define SRST_A_PHP_GIC_ITS 304
|
||||
#define SRST_A_MMU_PCIE 305
|
||||
#define SRST_A_MMU_PHP 306
|
||||
#define SRST_A_MMU_BIU 307
|
||||
|
||||
#define SRST_A_USB3OTG2 308
|
||||
|
||||
#define SRST_PMALIVE0 309
|
||||
#define SRST_PMALIVE1 310
|
||||
#define SRST_PMALIVE2 311
|
||||
#define SRST_A_SATA0 312
|
||||
#define SRST_A_SATA1 313
|
||||
#define SRST_A_SATA2 314
|
||||
#define SRST_RXOOB0 315
|
||||
#define SRST_RXOOB1 316
|
||||
#define SRST_RXOOB2 317
|
||||
#define SRST_ASIC0 318
|
||||
#define SRST_ASIC1 319
|
||||
#define SRST_ASIC2 320
|
||||
|
||||
#define SRST_A_RKVDEC_CCU 321
|
||||
#define SRST_H_RKVDEC0 322
|
||||
#define SRST_A_RKVDEC0 323
|
||||
#define SRST_H_RKVDEC0_BIU 324
|
||||
#define SRST_A_RKVDEC0_BIU 325
|
||||
#define SRST_RKVDEC0_CA 326
|
||||
#define SRST_RKVDEC0_HEVC_CA 327
|
||||
#define SRST_RKVDEC0_CORE 328
|
||||
|
||||
#define SRST_H_RKVDEC1 329
|
||||
#define SRST_A_RKVDEC1 330
|
||||
#define SRST_H_RKVDEC1_BIU 331
|
||||
#define SRST_A_RKVDEC1_BIU 332
|
||||
#define SRST_RKVDEC1_CA 333
|
||||
#define SRST_RKVDEC1_HEVC_CA 334
|
||||
#define SRST_RKVDEC1_CORE 335
|
||||
|
||||
#define SRST_A_USB_BIU 336
|
||||
#define SRST_H_USB_BIU 337
|
||||
#define SRST_A_USB3OTG0 338
|
||||
#define SRST_A_USB3OTG1 339
|
||||
#define SRST_H_HOST0 340
|
||||
#define SRST_H_HOST_ARB0 341
|
||||
#define SRST_H_HOST1 342
|
||||
#define SRST_H_HOST_ARB1 343
|
||||
#define SRST_A_USB_GRF 344
|
||||
#define SRST_C_USB2P0_HOST0 345
|
||||
|
||||
#define SRST_C_USB2P0_HOST1 346
|
||||
#define SRST_HOST_UTMI0 347
|
||||
#define SRST_HOST_UTMI1 348
|
||||
|
||||
#define SRST_A_VDPU_BIU 349
|
||||
#define SRST_A_VDPU_LOW_BIU 350
|
||||
#define SRST_H_VDPU_BIU 351
|
||||
#define SRST_A_JPEG_DECODER_BIU 352
|
||||
#define SRST_A_VPU 353
|
||||
#define SRST_H_VPU 354
|
||||
#define SRST_A_JPEG_ENCODER0 355
|
||||
#define SRST_H_JPEG_ENCODER0 356
|
||||
#define SRST_A_JPEG_ENCODER1 357
|
||||
#define SRST_H_JPEG_ENCODER1 358
|
||||
#define SRST_A_JPEG_ENCODER2 359
|
||||
#define SRST_H_JPEG_ENCODER2 360
|
||||
|
||||
#define SRST_A_JPEG_ENCODER3 361
|
||||
#define SRST_H_JPEG_ENCODER3 362
|
||||
#define SRST_A_JPEG_DECODER 363
|
||||
#define SRST_H_JPEG_DECODER 364
|
||||
#define SRST_H_IEP2P0 365
|
||||
#define SRST_A_IEP2P0 366
|
||||
#define SRST_IEP2P0_CORE 367
|
||||
#define SRST_H_RGA2 368
|
||||
#define SRST_A_RGA2 369
|
||||
#define SRST_RGA2_CORE 370
|
||||
#define SRST_H_RGA3_0 371
|
||||
#define SRST_A_RGA3_0 372
|
||||
#define SRST_RGA3_0_CORE 373
|
||||
|
||||
#define SRST_H_RKVENC0_BIU 374
|
||||
#define SRST_A_RKVENC0_BIU 375
|
||||
#define SRST_H_RKVENC0 376
|
||||
#define SRST_A_RKVENC0 377
|
||||
#define SRST_RKVENC0_CORE 378
|
||||
|
||||
#define SRST_H_RKVENC1_BIU 379
|
||||
#define SRST_A_RKVENC1_BIU 380
|
||||
#define SRST_H_RKVENC1 381
|
||||
#define SRST_A_RKVENC1 382
|
||||
#define SRST_RKVENC1_CORE 383
|
||||
|
||||
#define SRST_A_VI_BIU 384
|
||||
#define SRST_H_VI_BIU 385
|
||||
#define SRST_P_VI_BIU 386
|
||||
#define SRST_D_VICAP 387
|
||||
#define SRST_A_VICAP 388
|
||||
#define SRST_H_VICAP 389
|
||||
#define SRST_ISP0 390
|
||||
#define SRST_ISP0_VICAP 391
|
||||
|
||||
#define SRST_FISHEYE0 392
|
||||
#define SRST_FISHEYE1 393
|
||||
#define SRST_P_CSI_HOST_0 394
|
||||
#define SRST_P_CSI_HOST_1 395
|
||||
#define SRST_P_CSI_HOST_2 396
|
||||
#define SRST_P_CSI_HOST_3 397
|
||||
#define SRST_P_CSI_HOST_4 398
|
||||
#define SRST_P_CSI_HOST_5 399
|
||||
|
||||
#define SRST_CSIHOST0_VICAP 400
|
||||
#define SRST_CSIHOST1_VICAP 401
|
||||
#define SRST_CSIHOST2_VICAP 402
|
||||
#define SRST_CSIHOST3_VICAP 403
|
||||
#define SRST_CSIHOST4_VICAP 404
|
||||
#define SRST_CSIHOST5_VICAP 405
|
||||
#define SRST_CIFIN 406
|
||||
|
||||
#define SRST_A_VOP_BIU 407
|
||||
#define SRST_A_VOP_LOW_BIU 408
|
||||
#define SRST_H_VOP_BIU 409
|
||||
#define SRST_P_VOP_BIU 410
|
||||
#define SRST_H_VOP 411
|
||||
#define SRST_A_VOP 412
|
||||
#define SRST_D_VOP0 413
|
||||
#define SRST_D_VOP2HDMI_BRIDGE0 414
|
||||
#define SRST_D_VOP2HDMI_BRIDGE1 415
|
||||
|
||||
#define SRST_D_VOP1 416
|
||||
#define SRST_D_VOP2 417
|
||||
#define SRST_D_VOP3 418
|
||||
#define SRST_P_VOPGRF 419
|
||||
#define SRST_P_DSIHOST0 420
|
||||
#define SRST_P_DSIHOST1 421
|
||||
#define SRST_DSIHOST0 422
|
||||
#define SRST_DSIHOST1 423
|
||||
#define SRST_VOP_PMU 424
|
||||
#define SRST_P_VOP_CHANNEL_BIU 425
|
||||
|
||||
#define SRST_H_VO0_BIU 426
|
||||
#define SRST_H_VO0_S_BIU 427
|
||||
#define SRST_P_VO0_BIU 428
|
||||
#define SRST_P_VO0_S_BIU 429
|
||||
#define SRST_A_HDCP0_BIU 430
|
||||
#define SRST_P_VO0GRF 431
|
||||
#define SRST_H_HDCP_KEY0 432
|
||||
#define SRST_A_HDCP0 433
|
||||
#define SRST_H_HDCP0 434
|
||||
#define SRST_HDCP0 435
|
||||
|
||||
#define SRST_P_TRNG0 436
|
||||
#define SRST_DP0 437
|
||||
#define SRST_DP1 438
|
||||
#define SRST_H_I2S4_8CH 439
|
||||
#define SRST_M_I2S4_8CH_TX 440
|
||||
#define SRST_H_I2S8_8CH 441
|
||||
|
||||
#define SRST_M_I2S8_8CH_TX 442
|
||||
#define SRST_H_SPDIF2_DP0 443
|
||||
#define SRST_M_SPDIF2_DP0 444
|
||||
#define SRST_H_SPDIF5_DP1 445
|
||||
#define SRST_M_SPDIF5_DP1 446
|
||||
|
||||
#define SRST_A_HDCP1_BIU 447
|
||||
#define SRST_A_VO1_BIU 448
|
||||
#define SRST_H_VOP1_BIU 449
|
||||
#define SRST_H_VOP1_S_BIU 450
|
||||
#define SRST_P_VOP1_BIU 451
|
||||
#define SRST_P_VO1GRF 452
|
||||
#define SRST_P_VO1_S_BIU 453
|
||||
|
||||
#define SRST_H_I2S7_8CH 454
|
||||
#define SRST_M_I2S7_8CH_RX 455
|
||||
#define SRST_H_HDCP_KEY1 456
|
||||
#define SRST_A_HDCP1 457
|
||||
#define SRST_H_HDCP1 458
|
||||
#define SRST_HDCP1 459
|
||||
#define SRST_P_TRNG1 460
|
||||
#define SRST_P_HDMITX0 461
|
||||
|
||||
#define SRST_HDMITX0_REF 462
|
||||
#define SRST_P_HDMITX1 463
|
||||
#define SRST_HDMITX1_REF 464
|
||||
#define SRST_A_HDMIRX 465
|
||||
#define SRST_P_HDMIRX 466
|
||||
#define SRST_HDMIRX_REF 467
|
||||
|
||||
#define SRST_P_EDP0 468
|
||||
#define SRST_EDP0_24M 469
|
||||
#define SRST_P_EDP1 470
|
||||
#define SRST_EDP1_24M 471
|
||||
#define SRST_M_I2S5_8CH_TX 472
|
||||
#define SRST_H_I2S5_8CH 473
|
||||
#define SRST_M_I2S6_8CH_TX 474
|
||||
|
||||
#define SRST_M_I2S6_8CH_RX 475
|
||||
#define SRST_H_I2S6_8CH 476
|
||||
#define SRST_H_SPDIF3 477
|
||||
#define SRST_M_SPDIF3 478
|
||||
#define SRST_H_SPDIF4 479
|
||||
#define SRST_M_SPDIF4 480
|
||||
#define SRST_H_SPDIFRX0 481
|
||||
#define SRST_M_SPDIFRX0 482
|
||||
#define SRST_H_SPDIFRX1 483
|
||||
#define SRST_M_SPDIFRX1 484
|
||||
|
||||
#define SRST_H_SPDIFRX2 485
|
||||
#define SRST_M_SPDIFRX2 486
|
||||
#define SRST_LINKSYM_HDMITXPHY0 487
|
||||
#define SRST_LINKSYM_HDMITXPHY1 488
|
||||
#define SRST_VO1_BRIDGE0 489
|
||||
#define SRST_VO1_BRIDGE1 490
|
||||
|
||||
#define SRST_H_I2S9_8CH 491
|
||||
#define SRST_M_I2S9_8CH_RX 492
|
||||
#define SRST_H_I2S10_8CH 493
|
||||
#define SRST_M_I2S10_8CH_RX 494
|
||||
#define SRST_P_S_HDMIRX 495
|
||||
|
||||
#define SRST_GPU 496
|
||||
#define SRST_SYS_GPU 497
|
||||
#define SRST_A_S_GPU_BIU 498
|
||||
#define SRST_A_M0_GPU_BIU 499
|
||||
#define SRST_A_M1_GPU_BIU 500
|
||||
#define SRST_A_M2_GPU_BIU 501
|
||||
#define SRST_A_M3_GPU_BIU 502
|
||||
#define SRST_P_GPU_BIU 503
|
||||
#define SRST_P_GPU_PVTM 504
|
||||
|
||||
#define SRST_GPU_PVTM 505
|
||||
#define SRST_P_GPU_GRF 506
|
||||
#define SRST_GPU_PVTPLL 507
|
||||
#define SRST_GPU_JTAG 508
|
||||
|
||||
#define SRST_A_AV1_BIU 509
|
||||
#define SRST_A_AV1 510
|
||||
#define SRST_P_AV1_BIU 511
|
||||
#define SRST_P_AV1 512
|
||||
|
||||
#define SRST_A_DDR_BIU 513
|
||||
#define SRST_A_DMA2DDR 514
|
||||
#define SRST_A_DDR_SHAREMEM 515
|
||||
#define SRST_A_DDR_SHAREMEM_BIU 516
|
||||
#define SRST_A_CENTER_S200_BIU 517
|
||||
#define SRST_A_CENTER_S400_BIU 518
|
||||
#define SRST_H_AHB2APB 519
|
||||
#define SRST_H_CENTER_BIU 520
|
||||
#define SRST_F_DDR_CM0_CORE 521
|
||||
|
||||
#define SRST_DDR_TIMER0 522
|
||||
#define SRST_DDR_TIMER1 523
|
||||
#define SRST_T_WDT_DDR 524
|
||||
#define SRST_T_DDR_CM0_JTAG 525
|
||||
#define SRST_P_CENTER_GRF 526
|
||||
#define SRST_P_AHB2APB 527
|
||||
#define SRST_P_WDT 528
|
||||
#define SRST_P_TIMER 529
|
||||
#define SRST_P_DMA2DDR 530
|
||||
#define SRST_P_SHAREMEM 531
|
||||
#define SRST_P_CENTER_BIU 532
|
||||
#define SRST_P_CENTER_CHANNEL_BIU 533
|
||||
|
||||
#define SRST_P_USBDPGRF0 534
|
||||
#define SRST_P_USBDPPHY0 535
|
||||
#define SRST_P_USBDPGRF1 536
|
||||
#define SRST_P_USBDPPHY1 537
|
||||
#define SRST_P_HDPTX0 538
|
||||
#define SRST_P_HDPTX1 539
|
||||
#define SRST_P_APB2ASB_SLV_BOT_RIGHT 540
|
||||
#define SRST_P_USB2PHY_U3_0_GRF0 541
|
||||
#define SRST_P_USB2PHY_U3_1_GRF0 542
|
||||
#define SRST_P_USB2PHY_U2_0_GRF0 543
|
||||
#define SRST_P_USB2PHY_U2_1_GRF0 544
|
||||
#define SRST_HDPTX0_ROPLL 545
|
||||
#define SRST_HDPTX0_LCPLL 546
|
||||
#define SRST_HDPTX0 547
|
||||
#define SRST_HDPTX1_ROPLL 548
|
||||
|
||||
#define SRST_HDPTX1_LCPLL 549
|
||||
#define SRST_HDPTX1 550
|
||||
#define SRST_HDPTX0_HDMIRXPHY_SET 551
|
||||
#define SRST_USBDP_COMBO_PHY0 552
|
||||
#define SRST_USBDP_COMBO_PHY0_LCPLL 553
|
||||
#define SRST_USBDP_COMBO_PHY0_ROPLL 554
|
||||
#define SRST_USBDP_COMBO_PHY0_PCS_HS 555
|
||||
#define SRST_USBDP_COMBO_PHY1 556
|
||||
#define SRST_USBDP_COMBO_PHY1_LCPLL 557
|
||||
#define SRST_USBDP_COMBO_PHY1_ROPLL 558
|
||||
#define SRST_USBDP_COMBO_PHY1_PCS_HS 559
|
||||
#define SRST_HDMIHDP0 560
|
||||
#define SRST_HDMIHDP1 561
|
||||
|
||||
#define SRST_A_VO1USB_TOP_BIU 562
|
||||
#define SRST_H_VO1USB_TOP_BIU 563
|
||||
|
||||
#define SRST_H_SDIO_BIU 564
|
||||
#define SRST_H_SDIO 565
|
||||
#define SRST_SDIO 566
|
||||
|
||||
#define SRST_H_RGA3_BIU 567
|
||||
#define SRST_A_RGA3_BIU 568
|
||||
#define SRST_H_RGA3_1 569
|
||||
#define SRST_A_RGA3_1 570
|
||||
#define SRST_RGA3_1_CORE 571
|
||||
|
||||
#define SRST_REF_PIPE_PHY0 572
|
||||
#define SRST_REF_PIPE_PHY1 573
|
||||
#define SRST_REF_PIPE_PHY2 574
|
||||
|
||||
#define SRST_P_PHPTOP_CRU 575
|
||||
#define SRST_P_PCIE2_GRF0 576
|
||||
#define SRST_P_PCIE2_GRF1 577
|
||||
#define SRST_P_PCIE2_GRF2 578
|
||||
#define SRST_P_PCIE2_PHY0 579
|
||||
#define SRST_P_PCIE2_PHY1 580
|
||||
#define SRST_P_PCIE2_PHY2 581
|
||||
#define SRST_P_PCIE3_PHY 582
|
||||
#define SRST_P_APB2ASB_SLV_CHIP_TOP 583
|
||||
#define SRST_PCIE30_PHY 584
|
||||
|
||||
#define SRST_H_PMU1_BIU 585
|
||||
#define SRST_P_PMU1_BIU 586
|
||||
#define SRST_H_PMU_CM0_BIU 587
|
||||
#define SRST_F_PMU_CM0_CORE 588
|
||||
#define SRST_T_PMU1_CM0_JTAG 589
|
||||
|
||||
#define SRST_DDR_FAIL_SAFE 590
|
||||
#define SRST_P_CRU_PMU1 591
|
||||
#define SRST_P_PMU1_GRF 592
|
||||
#define SRST_P_PMU1_IOC 593
|
||||
#define SRST_P_PMU1WDT 594
|
||||
#define SRST_T_PMU1WDT 595
|
||||
#define SRST_P_PMU1TIMER 596
|
||||
#define SRST_PMU1TIMER0 597
|
||||
#define SRST_PMU1TIMER1 598
|
||||
#define SRST_P_PMU1PWM 599
|
||||
#define SRST_PMU1PWM 600
|
||||
|
||||
#define SRST_P_I2C0 601
|
||||
#define SRST_I2C0 602
|
||||
#define SRST_S_UART0 603
|
||||
#define SRST_P_UART0 604
|
||||
#define SRST_H_I2S1_8CH 605
|
||||
#define SRST_M_I2S1_8CH_TX 606
|
||||
#define SRST_M_I2S1_8CH_RX 607
|
||||
#define SRST_H_PDM0 608
|
||||
#define SRST_PDM0 609
|
||||
|
||||
#define SRST_H_VAD 610
|
||||
#define SRST_HDPTX0_INIT 611
|
||||
#define SRST_HDPTX0_CMN 612
|
||||
#define SRST_HDPTX0_LANE 613
|
||||
#define SRST_HDPTX1_INIT 614
|
||||
|
||||
#define SRST_HDPTX1_CMN 615
|
||||
#define SRST_HDPTX1_LANE 616
|
||||
#define SRST_M_MIPI_DCPHY0 617
|
||||
#define SRST_S_MIPI_DCPHY0 618
|
||||
#define SRST_M_MIPI_DCPHY1 619
|
||||
#define SRST_S_MIPI_DCPHY1 620
|
||||
#define SRST_OTGPHY_U3_0 621
|
||||
#define SRST_OTGPHY_U3_1 622
|
||||
#define SRST_OTGPHY_U2_0 623
|
||||
#define SRST_OTGPHY_U2_1 624
|
||||
|
||||
#define SRST_P_PMU0GRF 625
|
||||
#define SRST_P_PMU0IOC 626
|
||||
#define SRST_P_GPIO0 627
|
||||
#define SRST_GPIO0 628
|
||||
|
||||
#define SRST_A_SECURE_NS_BIU 629
|
||||
#define SRST_H_SECURE_NS_BIU 630
|
||||
#define SRST_A_SECURE_S_BIU 631
|
||||
#define SRST_H_SECURE_S_BIU 632
|
||||
#define SRST_P_SECURE_S_BIU 633
|
||||
#define SRST_CRYPTO_CORE 634
|
||||
|
||||
#define SRST_CRYPTO_PKA 635
|
||||
#define SRST_CRYPTO_RNG 636
|
||||
#define SRST_A_CRYPTO 637
|
||||
#define SRST_H_CRYPTO 638
|
||||
#define SRST_KEYLADDER_CORE 639
|
||||
#define SRST_KEYLADDER_RNG 640
|
||||
#define SRST_A_KEYLADDER 641
|
||||
#define SRST_H_KEYLADDER 642
|
||||
#define SRST_P_OTPC_S 643
|
||||
#define SRST_OTPC_S 644
|
||||
#define SRST_WDT_S 645
|
||||
|
||||
#define SRST_T_WDT_S 646
|
||||
#define SRST_H_BOOTROM 647
|
||||
#define SRST_A_DCF 648
|
||||
#define SRST_P_DCF 649
|
||||
#define SRST_H_BOOTROM_NS 650
|
||||
#define SRST_P_KEYLADDER 651
|
||||
#define SRST_H_TRNG_S 652
|
||||
|
||||
#define SRST_H_TRNG_NS 653
|
||||
#define SRST_D_SDMMC_BUFFER 654
|
||||
#define SRST_H_SDMMC 655
|
||||
#define SRST_H_SDMMC_BUFFER 656
|
||||
#define SRST_SDMMC 657
|
||||
#define SRST_P_TRNG_CHK 658
|
||||
#define SRST_TRNG_S 659
|
||||
|
||||
#define SRST_A_HDMIRX_BIU 660
|
||||
|
||||
#endif
|
||||
Executable → Regular
Executable → Regular
@@ -362,19 +362,6 @@
|
||||
&pcie2x1l0 {
|
||||
reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x00200000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rtl8125_1: pcie@20,0 {
|
||||
compatible = "pci10ec,8125";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
|
||||
realtek,led-data = <0x0 0x2b 0x200 0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2x1l1 {
|
||||
@@ -404,19 +391,6 @@
|
||||
&pcie2x1l2 {
|
||||
reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x00400000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rtl8125_2: pcie@40,0 {
|
||||
compatible = "pci10ec,8125";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
|
||||
realtek,led-data = <0x0 0x2b 0x200 0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
|
||||
-210
@@ -1,210 +0,0 @@
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -128,6 +128,11 @@
|
||||
opp-microvolt = <1050000 1050000 1150000>;
|
||||
};
|
||||
};
|
||||
+
|
||||
+ display_subsystem: display-subsystem {
|
||||
+ compatible = "rockchip,display-subsystem";
|
||||
+ ports = <&vop_out>;
|
||||
+ };
|
||||
|
||||
firmware {
|
||||
scmi: scmi {
|
||||
@@ -143,6 +148,56 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
+
|
||||
+ gpu_opp_table: opp-table-1 {
|
||||
+ compatible = "operating-points-v2";
|
||||
+
|
||||
+ opp-200000000 {
|
||||
+ opp-hz = /bits/ 64 <200000000>;
|
||||
+ opp-microvolt = <850000 850000 1000000>;
|
||||
+ };
|
||||
+
|
||||
+ opp-300000000 {
|
||||
+ opp-hz = /bits/ 64 <300000000>;
|
||||
+ opp-microvolt = <850000 850000 1000000>;
|
||||
+ };
|
||||
+
|
||||
+ opp-400000000 {
|
||||
+ opp-hz = /bits/ 64 <400000000>;
|
||||
+ opp-microvolt = <850000 850000 1000000>;
|
||||
+ };
|
||||
+
|
||||
+ opp-600000000 {
|
||||
+ opp-hz = /bits/ 64 <600000000>;
|
||||
+ opp-microvolt = <900000 900000 1000000>;
|
||||
+ };
|
||||
+
|
||||
+ opp-700000000 {
|
||||
+ opp-hz = /bits/ 64 <700000000>;
|
||||
+ opp-microvolt = <950000 950000 1000000>;
|
||||
+ };
|
||||
+
|
||||
+ opp-800000000 {
|
||||
+ opp-hz = /bits/ 64 <800000000>;
|
||||
+ opp-microvolt = <1000000 1000000 1000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ hdmi_sound: hdmi-sound {
|
||||
+ compatible = "simple-audio-card";
|
||||
+ simple-audio-card,name = "HDMI";
|
||||
+ simple-audio-card,format = "i2s";
|
||||
+ simple-audio-card,mclk-fs = <256>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ simple-audio-card,codec {
|
||||
+ sound-dai = <&hdmi>;
|
||||
+ };
|
||||
+
|
||||
+ simple-audio-card,cpu {
|
||||
+ sound-dai = <&i2s0_8ch>;
|
||||
+ };
|
||||
+ };
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a55-pmu";
|
||||
@@ -535,6 +590,21 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
+
|
||||
+ gpu: gpu@fde60000 {
|
||||
+ compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
|
||||
+ reg = <0x0 0xfde60000 0x0 0x4000>;
|
||||
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "job", "mmu", "gpu";
|
||||
+ clocks = <&scmi_clk 1>, <&cru CLK_GPU>;
|
||||
+ clock-names = "gpu", "bus";
|
||||
+ #cooling-cells = <2>;
|
||||
+ operating-points-v2 = <&gpu_opp_table>;
|
||||
+ power-domains = <&power RK3568_PD_GPU>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
|
||||
sdmmc2: mmc@fe000000 {
|
||||
compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
@@ -596,6 +666,53 @@
|
||||
queue0 {};
|
||||
};
|
||||
};
|
||||
+
|
||||
+ vop: vop@fe040000 {
|
||||
+ reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
|
||||
+ reg-names = "vop", "gamma-lut";
|
||||
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>,
|
||||
+ <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
|
||||
+ clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
|
||||
+ iommus = <&vop_mmu>;
|
||||
+ power-domains = <&power RK3568_PD_VO>;
|
||||
+ rockchip,grf = <&grf>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ vop_out: ports {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ vp0: port@0 {
|
||||
+ reg = <0>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ vp1: port@1 {
|
||||
+ reg = <1>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ vp2: port@2 {
|
||||
+ reg = <2>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vop_mmu: iommu@fe043e00 {
|
||||
+ compatible = "rockchip,rk3568-iommu";
|
||||
+ reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
|
||||
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
|
||||
+ clock-names = "aclk", "iface";
|
||||
+ #iommu-cells = <0>;
|
||||
+ power-domains = <&power RK3568_PD_VO>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
|
||||
qos_gpu: qos@fe128000 {
|
||||
compatible = "rockchip,rk3568-qos", "syscon";
|
||||
@@ -716,6 +833,38 @@
|
||||
compatible = "rockchip,rk3568-qos", "syscon";
|
||||
reg = <0x0 0xfe1a8100 0x0 0x20>;
|
||||
};
|
||||
+
|
||||
+ hdmi: hdmi@fe0a0000 {
|
||||
+ compatible = "rockchip,rk3568-dw-hdmi";
|
||||
+ reg = <0x0 0xfe0a0000 0x0 0x20000>;
|
||||
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru PCLK_HDMI_HOST>,
|
||||
+ <&cru CLK_HDMI_SFR>,
|
||||
+ <&cru CLK_HDMI_CEC>,
|
||||
+ <&pmucru CLK_HDMI_REF>,
|
||||
+ <&cru HCLK_VO>;
|
||||
+ clock-names = "iahb", "isfr", "cec", "ref";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
|
||||
+ power-domains = <&power RK3568_PD_VO>;
|
||||
+ reg-io-width = <4>;
|
||||
+ rockchip,grf = <&grf>;
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ ports {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ hdmi_in: port@0 {
|
||||
+ reg = <0>;
|
||||
+ };
|
||||
+
|
||||
+ hdmi_out: port@1 {
|
||||
+ reg = <1>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
|
||||
pcie2x1: pcie@fe260000 {
|
||||
compatible = "rockchip,rk3568-pcie";
|
||||
@@ -804,6 +953,23 @@
|
||||
clock-names = "clk_sfc", "hclk_sfc";
|
||||
pinctrl-0 = <&fspi_pins>;
|
||||
pinctrl-names = "default";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ i2s0_8ch: i2s@fe400000 {
|
||||
+ compatible = "rockchip,rk3568-i2s-tdm";
|
||||
+ reg = <0x0 0xfe400000 0x0 0x1000>;
|
||||
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
|
||||
+ assigned-clock-rates = <1188000000>, <1188000000>;
|
||||
+ clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
|
||||
+ clock-names = "mclk_tx", "mclk_rx", "hclk";
|
||||
+ dmas = <&dmac1 0>;
|
||||
+ dma-names = "tx";
|
||||
+ resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
|
||||
+ reset-names = "tx-m", "rx-m";
|
||||
+ rockchip,grf = <&grf>;
|
||||
+ #sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -0,0 +1,77 @@
|
||||
From 6731d2c9039fbe1ecf21915eab3acee0a999508a Mon Sep 17 00:00:00 2001
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Date: Fri, 10 Jul 2020 21:38:20 +0200
|
||||
Subject: [PATCH] rockchip: use system LED for OpenWrt
|
||||
|
||||
Use the SYS LED on the casing for showing system status.
|
||||
|
||||
This patch is kept separate from the NanoPi R2S support patch, as i plan
|
||||
on submitting the device support upstream.
|
||||
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 9 ++++++++-
|
||||
1 file changed, 8 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -6,6 +6,7 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
+#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "rk3328.dtsi"
|
||||
|
||||
@@ -16,6 +17,11 @@
|
||||
aliases {
|
||||
ethernet1 = &rtl8153;
|
||||
mmc0 = &sdmmc;
|
||||
+
|
||||
+ led-boot = &sys_led;
|
||||
+ led-failsafe = &sys_led;
|
||||
+ led-running = &sys_led;
|
||||
+ led-upgrade = &sys_led;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@@ -48,19 +54,22 @@
|
||||
pinctrl-names = "default";
|
||||
|
||||
lan_led: led-0 {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = LED_FUNCTION_LAN;
|
||||
gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
- label = "nanopi-r2s:green:lan";
|
||||
};
|
||||
|
||||
sys_led: led-1 {
|
||||
+ color = <LED_COLOR_ID_RED>;
|
||||
+ function = LED_FUNCTION_STATUS;
|
||||
gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
- label = "nanopi-r2s:red:sys";
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
wan_led: led-2 {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = LED_FUNCTION_WAN;
|
||||
gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
|
||||
- label = "nanopi-r2s:green:wan";
|
||||
};
|
||||
};
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
|
||||
@@ -13,6 +13,11 @@
|
||||
aliases {
|
||||
mmc0 = &sdmmc;
|
||||
mmc1 = &emmc;
|
||||
+
|
||||
+ led-boot = &power_led;
|
||||
+ led-failsafe = &power_led;
|
||||
+ led-running = &power_led;
|
||||
+ led-upgrade = &power_led;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@@ -10,6 +10,16 @@ userspace or following a kernel panic is always working.
|
||||
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
|
||||
@@ -335,7 +335,6 @@
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
- sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc_sd>;
|
||||
vqmmc-supply = <&vcc_sdio>;
|
||||
status = "okay";
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
@@ -121,6 +121,11 @@
|
||||
|
||||
@@ -0,0 +1,16 @@
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
@@ -19,6 +19,13 @@
|
||||
model = "FriendlyElec NanoPi R4S";
|
||||
compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399";
|
||||
|
||||
+ aliases {
|
||||
+ led-boot = &sys_led;
|
||||
+ led-failsafe = &sys_led;
|
||||
+ led-running = &sys_led;
|
||||
+ led-upgrade = &sys_led;
|
||||
+ };
|
||||
+
|
||||
/delete-node/ display-subsystem;
|
||||
|
||||
gpio-leds {
|
||||
+40
@@ -0,0 +1,40 @@
|
||||
From d2166e3b3680bd2b206aebf1e1ce4c0d346f3c50 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Fri, 19 May 2023 12:10:52 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Orange Pi R1
|
||||
Plus
|
||||
|
||||
Add OpenWrt's LED aliases for showing system status.
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
---
|
||||
.../dts/rockchip/rk3328-orangepi-r1-plus.dts | 17 +++++++++--------
|
||||
1 file changed, 9 insertions(+), 8 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
|
||||
@@ -17,6 +17,11 @@
|
||||
aliases {
|
||||
ethernet1 = &rtl8153;
|
||||
mmc0 = &sdmmc;
|
||||
+
|
||||
+ led-boot = &status_led;
|
||||
+ led-failsafe = &status_led;
|
||||
+ led-running = &status_led;
|
||||
+ led-upgrade = &status_led;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@@ -41,11 +46,10 @@
|
||||
gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
- led-1 {
|
||||
+ status_led: led-1 {
|
||||
function = LED_FUNCTION_STATUS;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
- linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
led-2 {
|
||||
+24
@@ -0,0 +1,24 @@
|
||||
From b46a530d12ada422b9d5b2b97059e0d3ed950b40 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Fri, 19 May 2023 12:38:04 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: add LED configuration to Orange Pi R1
|
||||
Plus
|
||||
|
||||
Add the correct value for the RTL8153 LED configuration register to
|
||||
match the blink behavior of the other port on the device.
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
|
||||
@@ -365,6 +365,7 @@
|
||||
rtl8153: device@2 {
|
||||
compatible = "usbbda,8153";
|
||||
reg = <2>;
|
||||
+ realtek,led-data = <0x87>;
|
||||
};
|
||||
};
|
||||
|
||||
+1
-1
@@ -17,8 +17,8 @@ Signed-off-by: hmz007 <hmz007@gmail.com>
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -7,6 +7,7 @@
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
+#include "rk3328-dram-default-timing.dtsi"
|
||||
#include "rk3328.dtsi"
|
||||
|
||||
Reference in New Issue
Block a user