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* style(simd): rename sse to avx * fix(exp,simd): apply the right avx512 constraints to a few methods * fix(exp,simd): apply the right avx512 constraints to a few methods
4.0 KiB
4.0 KiB
name, slug, sourceRef, category, subCategory, similarHelpers, position, signatures
| name | slug | sourceRef | category | subCategory | similarHelpers | position | signatures | |||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Clamp | clamp | exp/simd/math_avx.go#L453 | exp | simd |
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40 |
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Clamps each element in a collection between min and max values using SIMD instructions. The suffix (x2, x4, x8, x16, x32, x64) indicates the number of lanes processed simultaneously.
Requirements
- Go 1.26+ with
GOEXPERIMENT=simd - amd64 architecture only
CPU compatibility
| SIMD variant | Lanes | Required flags | Typical CPUs |
|---|---|---|---|
| AVX (xN) | 2-16 | avx |
All amd64 |
| AVX2 (xN) | 4-32 | avx2 |
Intel Haswell+, AMD Excavator+ |
| AVX-512 (xN) | 8-64 | avx512f |
Intel Skylake-X+, some Xeons |
Note
: Choose the variant matching your CPU's capabilities. Higher lane counts provide better performance but require newer CPU support.
// Using AVX2 variant (32 lanes at once) - Intel Haswell+ / AMD Excavator+
result := simd.ClampInt8x32([]int8{1, 5, 10, 15, 20}, 5, 15)
// []int8{5, 5, 10, 15, 15}
// Using AVX-512 variant (16 lanes at once) - Intel Skylake-X+
result := simd.ClampFloat32x16([]float32{0.5, 1.5, 2.5, 3.5}, 1.0, 3.0)
// []float32{1.0, 1.5, 2.5, 3.0}
// Using AVX variant (8 lanes at once) - works on all amd64
result := simd.ClampInt16x8([]int16{100, 150, 200, 250}, 120, 220)
// []int16{120, 150, 200, 220}
// Empty collection returns empty collection
result := simd.ClampUint32x4([]uint32{}, 10, 100)
// []uint32{}